Equalizer With Segmented Arithmetic Circuits for Bandwidth
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Solution Overview
Problem
Existing equalizers face challenges in securing sufficient bandwidth due to the difficulty in effectively summing feedback signals and input signals, leading to reduced performance in signal transmission between devices or chips.
Innovation Solution
The proposed equalizer employs multiple arithmetic circuits to generate and perform weighted summation of feedback signals, reducing the load on summers and ensuring a sufficient bandwidth by strategically receiving and processing feedback signals from different sampling circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single summer is used to sum feedback signals and input signal, then the circuit structure is simple, but the bandwidth of the summer cannot be sufficiently secured
Solution Approach 1:
The patent divides the single summer function into multiple arithmetic circuits (first arithmetic circuit, second arithmetic circuit, third arithmetic circuit, fourth arithmetic circuit). Each arithmetic circuit handles specific feedback signals separately, reducing the loading effect on each circuit and thereby securing sufficient bandwidth for signal processing while maintaining relatively simple circuit implementation.
2Ease of manufacture
If multiple feedback signals are summed through a single summer, then the circuit implementation is straightforward, but the loading capacitance and operating time increase
Solution Approach 1:
The patent segments the feedback signal processing into multiple parallel arithmetic circuits. Each circuit processes a subset of feedback signals independently, reducing the total loading capacitance on each circuit. This segmentation decreases the operating time required for signal processing while keeping the overall circuit implementation straightforward through modular design.
Solution Approach 2:
The patent implements dynamic signal routing where different feedback signals are selectively connected to different arithmetic circuits based on their timing and weighting requirements. This dynamic allocation optimizes the processing speed by preventing signal congestion and reducing the effective loading capacitance on each arithmetic circuit, thereby decreasing operating time.
3Device complexity
If feedback signals are directly connected to the summer, then the circuit configuration is simple, but the bandwidth is reduced due to loading effects
Solution Approach 1:
The patent configures multiple arithmetic circuits to receive different feedback signals separately rather than connecting all feedback signals to a single summer. This segmentation reduces the loading effect on each arithmetic circuit, preserving the bandwidth necessary for high-speed signal processing while maintaining a relatively simple overall circuit configuration through systematic signal distribution.
Solution Approach 2:
The patent introduces arithmetic circuits as intermediary elements between the feedback signals and the final summation process. These intermediary circuits buffer the feedback signals, reducing the direct loading effect on the summation node and thereby preserving bandwidth. The intermediaries enable high-speed signal processing while keeping the circuit configuration manageable.
Data Source
AI summary
Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.