Equalizing Circuit Using Inverted Pulses for High-Speed Data Signals
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Solution Overview
Problem
The increasing data transmission speeds in electronic devices are limited by constraints such as high integration, electrostatic discharge conditions, and inductor limitations, leading to reduced data transmission speed and increased chip size and cost.
Innovation Solution
An electronic device with a first and second equalizing circuit that generate phase-inverted and pulse-based signals to correct data signals, improving eye diagram performance by increasing the difference between logic high and low levels, thereby enhancing data transmission speed without increasing chip size or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission speed is increased, then communication performance is improved, but chip size and cost increase due to constraints of inductors and high integration
Solution Approach 1:
The patent extracts and eliminates inductors from the data transmission circuit by implementing a resistor-based equalizing circuit. The equalizing circuit uses only resistors (R1, R2, R3, R4) and capacitors to achieve signal equalization without requiring inductors, thereby reducing chip area while maintaining high data transmission speeds. This extraction of the inductor component directly resolves the contradiction between transmission speed and chip size.
Solution Approach 2:
The patent changes the circuit parameters by using resistor-based equalization instead of inductor-based equalization. The equalizing circuit adjusts signal characteristics through resistor ratios (R1/R2, R3/R4) and capacitor values, enabling high-speed data transmission without the physical constraints of inductors. This parameter change allows achieving high transmission speeds with reduced chip area.
2Speed
If data transmission speed is increased, then communication performance is improved, but cost increases due to constraints of inductors and high integration
Solution Approach 1:
The patent extracts inductors from the circuit design, replacing them with resistors and capacitors that are cheaper and easier to manufacture. Inductors are typically more expensive and have larger parasitic effects, while the resistor-based equalizing circuit uses standard components that reduce manufacturing cost. This extraction directly addresses the cost increase issue while maintaining high transmission speeds.
Solution Approach 2:
The patent replaces expensive inductors with cheaper resistor and capacitor components. These passive components are more cost-effective and have better manufacturing yield. The equalizing circuit achieves the same functional goal using inexpensive components, thereby reducing overall device cost while supporting high-speed data transmission.
3Reliability
If inductors are used for data transmission, then signal integrity is maintained, but chip size increases and integration is limited
Solution Approach 1:
The patent merges the equalization function with the existing data transmission path by integrating the equalizing circuit directly into the data output circuit. The equalizing circuit (using resistors R1-R4 and capacitors) is combined with the data signal path, eliminating the need for separate inductor-based equalization stages. This merging maintains signal integrity while reducing chip area through high integration.
Solution Approach 2:
The patent changes the equalization mechanism from inductor-based to resistor-capacitor-based. The RC time constants and resistor ratios are carefully designed to provide the necessary signal equalization for high-speed transmission. This parameter change maintains signal integrity through proper impedance matching and signal conditioning without requiring large inductor components.
Data Source
AI summary
An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.