Equi-Length TSV Interconnections for Stacked DRAM Skew Reduction
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Solution Overview
Problem
Existing semiconductor devices with stacked DRAM chips face challenges in minimizing skew between interconnections and reducing the load of interconnections, particularly between a control chip and controlled chips, due to the lack of efficient interconnection management.
Innovation Solution
The use of penetrating through substrate vias (TSVs) to form equi-length interconnections for data signal, data strobe, address, command, and clock signals, allowing for minimized skew and shared usage across chip groups to reduce interconnection load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If penetrating through substrate vias are used to connect stacked DRAM chips, then the length of interconnections is reduced, but skew between interconnections increases due to unequal path lengths
Solution Approach 1:
The patent segments the interconnection paths by providing different numbers of penetrating through substrate vias for different signal types. Data signal interconnections use a first number of vias while data mask signal interconnections use a second number of vias, creating segmented paths that compensate for length differences and reduce skew
Solution Approach 2:
The patent applies local quality by assigning different via configurations to different signal types based on their specific requirements. Data signals receive one configuration while data mask signals receive another, optimizing each signal path locally to achieve overall skew reduction
2Reliability
If separate interconnections are provided for each signal type, then signal integrity is maintained, but interconnection load and complexity increase
Solution Approach 1:
The patent merges interconnections by having multiple signal types share common penetrating through substrate vias. Data signals and data mask signals share common interconnection paths, reducing the total number of vias and interconnection complexity while maintaining signal integrity through proper timing control
3Adaptability or versatility
If control chip is spatially separated from controlled chips, then functional modularity is achieved, but interconnection length and skew increase
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection using penetrating through substrate vias. This allows the control chip to be spatially separated from controlled chips in the vertical dimension while maintaining short interconnection paths through the stack, reducing both length and skew
Data Source
AI summary
In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other.