Equivalence-Checked RTL Generation via Redundant Code Removal
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Solution Overview
Problem
RTL optimization is challenging due to the complexity of production RTL, making it difficult to determine optimal signal widths, multiplexor branch necessity, and operand relevance in logical operations, requiring substantial time and expertise.
Innovation Solution
Automatic generation of optimized RTL through redundant code removal by introducing local mutations and using equivalence checking tools to confirm functionality, allowing for the trimming of unreachable or constant code without human intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual RTL optimization is performed by designers, then design quality and optimization precision can be improved, but time consumption and operational complexity increase significantly
Solution Approach 1:
The system performs self-optimization by automatically analyzing RTL code, identifying redundant operations, and generating optimized code without human intervention. The equivalence checker validates the optimized code to ensure functional correctness, enabling the system to serve itself in the optimization process.
Solution Approach 2:
Manual mechanical optimization efforts by designers are replaced with an automated computational system that uses equivalence checking and formal verification methods to perform RTL optimization, substituting human manual work with machine-based automated analysis and transformation.
2Manufacturing precision
If comprehensive RTL analysis is performed to determine optimal signal widths and multiplexor branches, then manufacturing precision improves, but device complexity and operational difficulty increase
Solution Approach 1:
An equivalence checking tool acts as an intermediary between the complex RTL code and the optimization process. This intermediary automatically analyzes the code, determines signal width requirements, identifies necessary multiplexor branches, and validates optimizations without requiring designers to directly engage with the complexity.
Solution Approach 2:
The system creates and analyzes copies of the RTL code through formal verification models and equivalence checking representations, allowing comprehensive analysis of signal widths and control logic without directly modifying or complicating the original design code.
3Productivity
If redundant code is removed automatically through local mutations, then productivity and automation extent improve, but reliability may be compromised without proper verification
Solution Approach 1:
The equivalence checking tool provides feedback by automatically verifying that optimized RTL code produces identical results to the original code. This feedback mechanism ensures that productivity-generating optimizations do not compromise reliability, as any functional deviations are detected and corrected.
Solution Approach 2:
Equivalence checking is performed preliminarily before finalizing the optimized code. The system pre-validates the correctness of optimizations by comparing the behavior of original and optimized code, ensuring reliability is maintained before the optimized code is accepted and deployed.
Data Source
AI summary
Described herein is a technique for automatic generation of optimized RTL via redundant code removal. By automatically introducing local mutations into the original RTL and using equivalence checking tools to confirm that the functionality it is not affected, optimized RTL can be produced automatically without requiring human intervention.