Equivalence Checking Using Correlation Information
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Solution Overview
Problem
Current methods for checking the equivalence of behavioral and RTL descriptions in semiconductor design are inefficient, leading to increased processing time and potential bugs due to the complexity of behavioral synthesis systems, which can result in rework and increased development time.
Innovation Solution
The use of correlation information generated from flip-flops with feedback loops and backward data dependence in the synthesis result, along with symbolic simulation, to partition and simplify the equivalence checking process, thereby reducing the verification scope and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive equivalence checking is performed between behavioral description and RTL description, then verification reliability is improved, but processing time increases significantly
Solution Approach 1:
The patent segments the equivalence checking process into multiple phases: pre-processing to extract correlation information between variables and registers, main equivalence checking using the extracted correlation, and post-processing. This segmentation allows the system to handle complex descriptions by breaking them into manageable parts and using the extracted correlation information to guide the checking process, thereby reducing overall processing time while maintaining verification reliability.
Solution Approach 2:
The patent performs preliminary actions by extracting correlation information between variables in the behavioral description and registers in the RTL description before the main equivalence checking process. This pre-extraction of correlation data enables the system to prepare necessary mapping information in advance, which speeds up the subsequent equivalence checking without compromising the thoroughness of verification.
2Adaptability or versatility
If behavioral synthesis system scope is expanded, then design capability is improved, but bug introduction probability increases
Solution Approach 1:
The patent implements feedback mechanisms through equivalence checking that verify the correctness of synthesized RTL descriptions against the original behavioral descriptions. This feedback loop detects bugs introduced during synthesis, allowing designers to identify and correct errors before they propagate to subsequent design stages, thereby maintaining reliability even as the synthesis system scope expands.
Solution Approach 2:
The patent uses disposable correlation information extracted during pre-processing to guide the equivalence checking process. This extracted correlation data serves as a temporary but effective guide that enables thorough verification without requiring complex, long-term maintenance of the checking system itself, allowing the system to handle expanded synthesis capabilities efficiently.
3Manufacturing precision
If equivalence checking covers all input sequences and output timings, then checking completeness is improved, but processing complexity increases
Solution Approach 1:
The patent changes parameters by extracting and utilizing correlation information that maps variables to registers and identifies data dependence relationships. This parameter transformation simplifies the checking process by providing structured mapping information that guides the equivalence verification, allowing complete checking of all input sequences and output timings without proportionally increasing processing complexity.
Data Source
AI summary
Specific characteristics of a branch structure between a behavioral description and a hardware description, a structural dependence relation therebetween, and the like are extracted and used to shorten the time of processing for equivalence checking, thereby contributing to the shortening of a processing time required for equivalence checking for a high-level description and a behavioral synthesis result. Upon checking of the equivalence of a high-level description and a synthesis result obtained by performing a behavior synthesis on the high-level description according to a behavioral synthesis restriction, correspondence information between flip-flops with a feedback loop in the synthesis result and variables associated therewith with a backward data dependence relation in a high-level description is generated and used.