Equivalence Checking Data Flow Graph Structural Analysis
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Solution Overview
Problem
The complexity of modern semiconductor circuits makes it difficult to verify that lower-level designs match the specifications and intended logic functions, especially when designs are optimized for specific parameters and do not share a one-to-one correspondence across different levels of abstraction, leading to challenges in ensuring equivalence and performance.
Innovation Solution
A computer-implemented method using equivalence checking that involves obtaining word-level and bit-level data flow graphs, searching for partial-product encoding, removing redundancy, and performing structural analysis to reduce and partition these graphs for verification, including generating a reference model and using binary decision diagrams to identify and cut nodes corresponding to partial-product encoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If structural analysis and graph reduction techniques are applied to simplify equivalence checking, then verification speed and accuracy are improved, but the complexity of the verification process increases
Solution Approach 1:
The verification process segments the complex equivalence checking task into distinct phases: obtaining word-level and bit-level data flow graphs, searching for partial-product encoding, removing redundancy, reducing graphs by finding adders, and performing final equivalence checking. This segmentation allows each phase to be optimized independently, improving overall verification accuracy while managing process complexity through structured organization.
2Productivity
If manual construction is used to optimize for certain parameters, then performance and physical size are improved, but verification equivalence between different abstractions becomes more difficult
Solution Approach 1:
The patent introduces data flow graphs as an intermediary representation that bridges word-level and bit-level designs. By converting both designs into DFG format and applying structural analysis, the method creates a common verification framework that maintains equivalence reliability even when manual optimization is used, allowing verification without requiring one-to-one correspondence between original abstractions.
3Adaptability or versatility
If design complexity increases to meet market demands, then system versatility and feature sets are improved, but verification difficulty and cost increase
Solution Approach 1:
The method performs preliminary structural analysis on data flow graphs before equivalence checking, including searching for partial-product encoding, removing redundancy, and reducing graphs by identifying adders. These preliminary actions simplify the verification task in advance, making it feasible to verify complex designs with high versatility without proportionally increasing verification difficulty or cost.
Data Source
AI summary
A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description.