Equivalence Checking via Data-Flow Graphs and Timesteps
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Solution Overview
Problem
Current methods for determining equivalence between high-level models (HLMs) and register transfer level models (RTLMs) are inefficient, particularly for large-scale designs, and lack effective formal approaches for verifying equivalence, leading to potential discrepancies and errors in hardware design validation.
Innovation Solution
A novel equivalency testing system that converts both HLMs and RTLMs into data-flow graphs (DFGs), uses symbolic simulation to generate timestep forms, and employs a combining structure to prove equivalence through inductive theorem proving with symbolic data values and conditional equivalence relations, ensuring accurate equivalence checking across all timesteps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive simulations are run to determine equivalence between RTLM and HLM, then coverage of design scenarios is improved, but time consumption increases significantly
Solution Approach 1:
The patent segments the equivalence verification process into formal analysis of individual timesteps rather than running extensive simulations across all possible scenarios. By dividing the verification into discrete, analyzable units (timesteps with specific input combinations), the method achieves comprehensive coverage without the exponential time cost of exhaustive simulation.
Solution Approach 2:
The patent performs preliminary actions by systematically generating all possible timesteps and their input combinations before execution. The formal analysis framework pre-computes the verification structure, including all relevant state transitions and output comparisons, enabling efficient batch processing that avoids iterative simulation overhead.
2Reliability
If formal analysis is applied to large-scale designs, then equivalence proof capability is improved, but computational efficiency deteriorates
Solution Approach 1:
The patent applies segmentation by breaking down large-scale design verification into manageable timestep units. Each timestep represents a discrete verification case that can be analyzed independently, allowing the formal method to scale to large designs by processing verification tasks in systematic batches rather than as monolithic analysis.
Solution Approach 2:
The patent changes parameters by representing design states and transitions in a formalized mathematical framework with defined timesteps, input combinations, and state variables. This parameter transformation enables automated formal analysis tools to efficiently process large-scale designs through systematic exploration of the state space rather than exhaustive simulation.
3Adaptability or versatility
If manual refinement from HLM to RTLM is performed, then design flexibility is maintained, but error probability increases
Solution Approach 1:
The patent implements feedback by establishing a formal verification loop that automatically checks equivalence between HLM and RTLM after manual refinement. The systematic timestep analysis provides immediate feedback on whether the RTLM correctly implements the HLM specification, allowing designers to detect and correct errors while maintaining design flexibility.
Solution Approach 2:
The patent introduces an intermediary formal verification framework that mediates between the manual refinement process and equivalence validation. This intermediary layer automatically analyzes the refined RTLM against the original HLM specification using systematic timestep analysis, bridging the gap between design flexibility and verification reliability.
Data Source
AI summary
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts [t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts [t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.