Equivalency Testing System Using Data-Flow Graphs
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Solution Overview
Problem
The existing methods for determining equivalence between high-level models (HLMs) and register transfer level models (RTLMs) are inefficient, particularly for large-scale designs, and lack effective formal analysis tools to verify equivalence, leading to potential discrepancies and errors in hardware design validation.
Innovation Solution
A novel equivalency testing system that converts both HLMs and RTLMs into data-flow graphs (DFGs), uses symbolic simulation to determine initial states, and employs a combining structure to prove equivalence through inductive theorem proving, utilizing symbolic data values and conditional equivalence relations to propagate values and detect equivalence across timesteps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional formal analysis approaches are applied to determine equivalence between RTLMs and HLMs, then measurement precision is improved, but productivity deteriorates due to inefficiency in large-scale designs
Solution Approach 1:
The verification process is segmented into three main phases: (1) conversion of RTLM and HLM into data-flow graphs, (2) symbolic simulation to determine initial states, and (3) inductive theorem proving to verify equivalence. This segmentation allows each phase to be optimized independently, improving overall productivity while maintaining precision.
Solution Approach 2:
Data-flow graphs serve as an intermediary representation between the RTLM and HLM, enabling formal analysis without directly comparing the complex original models. This intermediary structure simplifies the equivalence verification process, making it more efficient for large-scale designs while maintaining measurement precision.
2Productivity
If extensive simulations are run to determine equivalence between RTLMs and HLMs, then productivity is improved through automation, but measurement precision deteriorates due to missed subtle discrepancies
Solution Approach 1:
The patent replaces mechanical simulation-based verification with a formal mathematical approach using symbolic simulation and inductive theorem proving. This substitution eliminates the imprecision of simulation while maintaining high automation, as the formal methods can be automatically applied to verify equivalence without manual intervention.
Solution Approach 2:
The verification approach changes from using concrete simulation values to using symbolic parameters that represent all possible input combinations. This allows the system to prove equivalence for all cases simultaneously rather than testing individual scenarios, improving both precision and automation.
3Device complexity
If manual refinement is used to produce RTLMs from HLMs, then device complexity is reduced through simplicity of process, but reliability deteriorates due to error-proneness
Solution Approach 1:
The system performs self-verification by automatically converting HLMs to RTLMs and then using formal methods to verify that the conversion maintains equivalence. This self-service approach reduces reliance on manual checking while improving reliability through mathematical proof of correctness.
Solution Approach 2:
The patent implements a feedback loop where the converted RTLM is automatically verified against the original HLM using formal methods. If discrepancies are found, the process can be repeated with corrections, ensuring high reliability while maintaining process simplicity through automation.
Data Source
AI summary
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLMts and HLMts. A test bench CSts is selected that couples RTLMts and HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.