Equivalent Time Sampling System for OTDR
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Solution Overview
Problem
Existing OTDR systems require calibration and are prone to inaccuracies due to analog hardware and temperature drift, necessitating precise calibration and high-speed components for fine time base resolution across varying fiber lengths.
Innovation Solution
Employing two phase locked frequency sources for stimulus and sampling, allowing for equivalent time sampling with a wide range of pulse repetition rates and time steps, eliminating the need for calibration and using digital phase locked loops to ensure precise timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an analog adjustable time delay circuit is used to achieve fine time base resolution, then the time measurement precision is improved, but the system becomes subject to temperature induced inaccuracy and requires calibration
Solution Approach 1:
The patent replaces the analog adjustable time delay circuit with a digitally controlled delay mechanism. The delay is achieved by controlling the timing of pulse generation and sampling using digital counters and phase-locked loops, eliminating the temperature-sensitive analog components while maintaining fine time base resolution through digital precision.
Solution Approach 2:
The patent changes the control parameter from analog voltage adjustment to digital counting values. The time delay is controlled by programmable parameters in the digital domain, allowing precise control of time intervals without the temperature drift inherent in analog circuits. The system uses digital signal processing to maintain stable timing parameters across temperature variations.
2Measurement precision
If high speed, precision analog hardware is used to achieve fine time base resolution, then the measurement precision is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent substitutes complex high-speed analog hardware with digital electronics. Instead of using precision analog components like high-speed comparators and adjustable delay circuits, the system employs digital counters, phase-locked loops, and programmable logic to achieve the same timing precision with greater stability and reduced complexity.
Solution Approach 2:
The patent uses digital sampling and equivalent-time reconstruction to create a digital copy of the analog signal behavior. By sampling at lower speeds and using digital processing to reconstruct the timing information, the system achieves fine time base resolution without requiring high-speed analog hardware, thereby reducing device complexity.
3Measurement precision
If calibration procedures are implemented to correct component variations, then the measurement precision is improved, but the ease of operation is reduced
Solution Approach 1:
The patent implements self-calibrating digital circuits that automatically compensate for component variations without requiring external calibration procedures. The digital phase-locked loops and counters inherently maintain synchronization and timing accuracy through their digital nature, eliminating the need for manual calibration while preserving measurement precision.
Solution Approach 2:
The patent uses digital feedback mechanisms where the system continuously monitors its own timing parameters and automatically adjusts to maintain precision. The phase-locked loops provide automatic frequency and phase synchronization, and the digital processing continuously corrects for any drift, eliminating the need for external calibration while maintaining high measurement accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved step size precision, reduces temperature drift, and eliminates the need for calibration, resulting in a more accurate and efficient OTDR system capable of handling diverse fiber lengths without hardware inaccuracies.
Implementation Method 1
Employing two phase locked frequency sources for stimulus and sampling
Data Source
AI summary
An equivalent time sampling system employs two clock frequency sources, phase locked, wherein an analog to digital converter sampling clock is derived from one source and a pulse generator clock is derived from the other. Choice of the clock frequencies determines minimum time step and the set of available time steps, and pulse repetition period determines the time step size, for equivalent time sampling. The system is suitably implemented in a time domain reflectometer, optical time domain reflectometry system, or other systems for obtaining time domain responses to a periodic stimulus of a system under test, with stimulus rate and the sampling intervals varying over a wide range.