Erasable Non-Volatile Memory Cell With Metallic Erase Line
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Solution Overview
Problem
Conventional erasable programmable non-volatile memory devices face challenges in reducing size while avoiding punch-through effects during erase operations, which necessitate larger memory cell sizes and inefficient hot carrier ejection.
Innovation Solution
The memory cell design includes a metallic erase line positioned above the edge or corner of the floating gate, utilizing a blocking layer for point discharge effects to efficiently eject hot carriers during erase operations, thereby reducing cell size and improving erase efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase gate region is arranged to eject hot carriers during erase operation, then erase function is achieved, but punch-through effect occurs in the substrate requiring larger isolation structure width
Solution Approach 1:
A blocking layer is introduced as an intermediary between the erase gate and the substrate. This blocking layer prevents the punch-through effect by blocking the harmful carrier flow through the substrate while still allowing the erase gate to effectively eject hot carriers from the floating gate, thus resolving the contradiction between achieving reliable erase operation and avoiding substrate damage
2Object-affected harmful factors
If the isolation structure width is increased to avoid punch-through effect, then substrate protection is improved, but memory cell size increases
Solution Approach 1:
The blocking layer serves as a thin intermediary film that provides effective protection against punch-through effect without requiring a wide isolation structure. This allows the memory cell to maintain a compact size while still preventing substrate damage during erase operations, resolving the contradiction between substrate protection and cell size reduction
3Object-affected harmful factors
If the floating gate extension length is increased to avoid punch-through effect, then substrate protection is improved, but memory cell size increases
Solution Approach 1:
The blocking layer is positioned between the floating gate and substrate, eliminating the need for extended floating gate structures to prevent punch-through. This allows the floating gate to maintain a compact length while still achieving effective substrate protection, resolving the contradiction between punch-through prevention and floating gate dimension reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for effective hot carrier ejection and reduced memory cell size by leveraging a point discharge effect, enhancing erase operation efficiency and minimizing punch-through risks.
Implementation Method 1
utilizing a blocking layer for point discharge effects to efficiently eject hot carriers during erase operations
Data Source
AI summary
An erasable programmable non-volatile memory includes a first-type well region, three doped regions, two gate structures, a blocking layer and an erase line. The first doped region is connected with a source line. The third doped region is connected with a bit line. The first gate structure is spanned over an area between the first doped region and the second doped region. A first polysilicon gate of the first gate structure is connected with a select gate line. The second gate structure is spanned over an area between the second doped region and the third doped region. The second gate structure includes a floating gate and the floating gate is covered by the blocking layer. The erase line is contacted with the blocking layer. The erase line is located above an edge or a corner of the floating gate.