Erasable Non-Volatile Memory Cell With Program-Assisted Metal Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional erasable programmable non-volatile memories have a large size due to their twin-well structure, and they require inefficient electron injection mechanisms during programming cycles.
Innovation Solution
The introduction of a program-assisted metal layer over the floating gate, which receives a bias voltage to enhance electron injection into the floating gate, thereby improving programming capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a twin-well structure is used in conventional erasable programmable non-volatile memory, then the memory can achieve basic programming and erasing functions, but the overall size of the memory becomes large
Solution Approach 1:
The patent merges the programming and erasing functions into a single well structure. The first transistor (select transistor) and second transistor (floating gate transistor) are both constructed in the same n-well region, eliminating the need for separate p-well and n-well regions. This consolidation reduces the overall memory cell area while maintaining the ability to perform both programming and erasing operations through coordinated voltage applications to the select gate and floating gate.
Solution Approach 2:
The single n-well region serves multiple functions: it hosts both the select transistor and floating gate transistor, provides the substrate for charge storage, and enables both programming and erasing modes. The floating gate structure itself serves dual purposes as both the control element for the second transistor and the charge storage medium for non-volatile memory functionality.
2Reliability
If conventional electron injection mechanisms are used during programming cycles, then the basic programming function is achieved, but the electron injection efficiency is low
Solution Approach 1:
The patent introduces a program-assisted metal layer as an intermediary structure between the select gate and the floating gate. This metal layer, positioned adjacent to the floating gate, acts as a mediator to enhance the electric field during programming operations. By applying a bias voltage to the program-assisted metal layer, the electric field is concentrated and intensified, thereby improving hot carrier generation and electron injection into the floating gate without requiring higher overall voltages.
Solution Approach 2:
The program-assisted metal layer creates a localized enhancement of the electric field specifically at the region adjacent to the floating gate where electron injection occurs. Rather than uniformly increasing the electric field across the entire device, the metal layer focuses the field enhancement locally at the critical interface, improving injection efficiency while minimizing overall power consumption and avoiding breakdown in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the number of electrons injected into the floating gate, leading to enhanced programming efficiency and reduced memory cell size by optimizing the ratio of the program-assisted metal layer to the floating gate area.
Implementation Method 1
During the program cycle, a bias voltage is provided to the program-assisted metal layer. Consequently, the number of electrons (e.g. hot carriers) to be injected into the floating gate is increased
Implementation Method 2
the electrons (e.g. hot carriers) are injected into the floating gate 36 and are stored in the floating gate 36
Implementation Method 3
the electrons (e.g. hot carriers) are injected into the floating gate 36 and are stored in the floating gate 36. Consequently, the program action is completed
Implementation Method 4
The electrons stored in the floating gate are removed from the floating gate 36 and discharged out of the nonvolatile memory through the n-type doped region 38
Data Source
Figure 1A~1D
Figure 2A
Figure 2B
AI summary
An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.