Erasable Single-Poly Nonvolatile Memory With Segmented Gate
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Solution Overview
Problem
Conventional single-poly nonvolatile memories are limited to one-time programming (OTP) due to the inability to efficiently erase stored carriers from the floating gate, making them unsuitable for multi-times programming (MTP) applications, and their fabrication process is not compatible with standard CMOS manufacturing.
Innovation Solution
An erasable programmable single-poly nonvolatile memory design that includes a select gate, p-type doped regions, a floating gate, and an erase gate region, where the erase gate region is connected to an erase line voltage, allowing for the removal of stored carriers from the floating gate, and the transistors are constructed in an N-well region compatible with CMOS manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional single-poly nonvolatile memory is used, then fabrication is compatible with standard CMOS manufacturing process, but the memory can only be programmed once (OTP) and cannot be erased for multi-times programming (MTP)
Solution Approach 1:
The gate structure is segmented into two independent gates: a control gate (CG) for programming operations and an erase gate (EG) for erasure operations. This segmentation allows separate control of programming and erasing functions, enabling MTP capability while maintaining CMOS compatibility. The control gate receives control voltage (VCG) for carrier injection, while the erase gate receives erase voltage (VEG) for carrier removal, solving the fundamental limitation of conventional single-gate floating gate memories.
2Reliability
If dual-poly structure with separate control gate and floating gate is used, then erasable programmable functionality is achieved, but the fabrication process becomes complex and incompatible with standard CMOS manufacturing
Solution Approach 1:
The invention merges the control gate and floating gate functions into a single integrated gate structure formed by one continuous polysilicon layer. This merged structure is created using standard CMOS single-poly technology, eliminating the need for separate poly1 and poly2 layers. The single gate simultaneously provides the control gate region (for programming) and erase gate region (for erasing), simplifying fabrication while maintaining erasable programmable functionality.
3Ease of manufacture
If conventional single-poly OTP memory structure is used, then CMOS compatibility is maintained, but the inability to erase stored carriers prevents multi-times programming applications
Solution Approach 1:
The single polysilicon gate structure serves multiple functions: it acts as both the control gate for programming operations and the erase gate for erasure operations. By applying different voltages to different regions of the same gate structure (VCG to control gate, VEG to erase gate), the device achieves both programming and erasing capabilities within a unified CMOS-compatible architecture, enabling MTP applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables multi-times programming capability by effectively erasing and reprogramming the memory, maintaining distinguishable read currents across storage states even after numerous cycles, and is compatible with standard CMOS manufacturing processes.
Implementation Method 1
an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage (VEL)... allowing for the removal of stored carriers from the floating gate
Implementation Method 2
during the electrons are transmitted from the source line S to the drain line D through an n-channel region, the hot carriers (e.g. hot electrons) are attracted by the control voltage on the control gate 12 and injected into the floating gate 14
Data Source
AI summary
An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.