Erasable Single-Poly Nonvolatile Memory via Segmented Gate
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Solution Overview
Problem
Conventional single-poly nonvolatile memories are limited to one-time programming (OTP) due to the inability to efficiently erase carriers from the floating gate, making them unsuitable for multi-times programming (MTP) applications, and their fabrication process is not compatible with standard CMOS manufacturing.
Innovation Solution
An erasable programmable single-poly nonvolatile memory design that includes a substrate structure with PMOS transistors, a floating gate, and an erase gate region, allowing for the removal of stored carriers by applying specific voltage biases, enabling multiple programming cycles and compatibility with CMOS manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dual-poly structure with separate control gate and floating gate is used, then programming capability is achieved, but fabrication process complexity increases and CMOS compatibility is lost
Solution Approach 1:
The patent merges the control gate and floating gate into a single polysilicon gate structure. The gate is divided into two functional regions (first gate region and second gate region) but constructed as one continuous polysilicon layer, eliminating the need for separate gate fabrication processes while maintaining the dual-gate functionality for programming and erasing operations
Solution Approach 2:
The single polysilicon gate serves multiple functions: the first gate region functions as the control gate for programming, the second gate region functions as the floating gate for charge storage, and the unified structure enables compatibility with standard CMOS fabrication processes, making the device universally manufacturable
2Ease of manufacture
If a single-poly structure is used, then CMOS compatibility is achieved, but the ability to erase carriers from the floating gate is lost
Solution Approach 1:
The single polysilicon gate is segmented into two distinct functional regions: the first gate region that controls carrier injection and the second gate region that stores carriers. This segmentation allows independent voltage control of each region, enabling both programming (via the first gate) and erasing (via the second gate) operations while maintaining CMOS compatibility
Solution Approach 2:
The patent introduces an intermediate structure where the single polysilicon gate acts as both the control interface and the storage medium. By applying different voltages to different portions of the gate, the system mediates between the conflicting requirements of simplicity (single-poly) and functionality (erasable capability)
3Device complexity
If OTP memory structure is used, then fabrication simplicity is maintained, but multi-times programming capability is lost
Solution Approach 1:
The patent introduces dynamic voltage control to the single polysilicon gate structure. By dynamically applying different voltage polarities and magnitudes to the first and second gate regions, the memory can be programmed and erased repeatedly, transforming a static OTP structure into a dynamic MTP structure while keeping the fabrication simple
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for reversible storage states, enhancing the memory's functionality by enabling multiple programming cycles while maintaining compatibility with standard CMOS processes, thus overcoming the limitations of OTP memories.
Implementation Method 1
allowing for the removal of stored carriers by applying specific voltage biases
Implementation Method 2
the hot carriers (e.g. hot electrons) are attracted by the control voltage on the control gate 12 and injected into the floating gate 14
Data Source
AI summary
An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.