Erase Cycle Counting in Non-Volatile Memory Blocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices lack a method to track and manage the cycling of partitions, leading to potential uneven wear and reduced lifetime, as internal software cannot effectively monitor and adjust programming voltages based on cycle counts.
Innovation Solution
Implementing cycle counter rows in each block of the memory device allows internal software to track the number of cycles each partition has undergone, enabling adjustments to program voltages and verifying voltage levels based on cycle counts to improve reliability and extend memory lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cycle counter rows are implemented in each block, then reliability is improved through even wear distribution, but device complexity increases due to additional memory structures
Solution Approach 1:
The memory device is divided into multiple blocks, and each block is further segmented into partitions. Cycle counter rows are implemented at the block level to track erase cycles for each partition independently. This segmentation allows wear to be tracked and managed at a granular level, enabling the system to identify and redistribute workloads from heavily worn partitions to less worn ones, thereby improving overall reliability without requiring cycle tracking at the individual cell level.
Solution Approach 2:
Cycle counter rows serve as an intermediary structure between the control logic and the memory cells. These dedicated counter rows store cycle count information that the control logic uses to make intelligent decisions about workload distribution. The counters act as a mediator that provides wear information without requiring direct monitoring of each memory cell, simplifying the overall system while improving reliability through informed load balancing.
2Reliability
If cycle tracking is implemented at the block level, then wear management capability is improved, but manufacturing complexity increases
Solution Approach 1:
The cycle counter rows use the same memory cell structure and manufacturing process as the main memory array. The counters are implemented using identical transistors, word lines, and bit lines, allowing them to be fabricated simultaneously with the memory cells in the same process run. This multi-functionality approach enables the counters to serve wear tracking purposes while maintaining compatibility with existing manufacturing workflows, avoiding the need for separate specialized fabrication processes.
3Reliability
If partition cycling is monitored, then data integrity is improved through even wear distribution, but measurement precision requirements increase
Solution Approach 1:
The cycle count information is stored in dedicated counter rows that are separate from the main data storage areas. Each counter row maintains a copy of the erase cycle count for its associated partition. This copying mechanism ensures that cycle count data is preserved independently from user data, preventing corruption of wear information even if data cells experience degradation. The control logic reads these copied counter values to make wear-balancing decisions, ensuring accurate measurement without compromising data integrity.
Data Source
AI summary
Erase cycle counting may be used for a non-volatile memory to balance the cycles on memory blocks or partitions. In some embodiments, the non-volatile memory may include two memory locations such as wordlines associated with each block of memory. The wordlines may be alternately erased so that an updated cycle count is transferred from the wordlines to the other. In the case of a power loss in the course of the updating of the cycle count, a method may detect that the data is in improper states and require that the erase be restarted after the power loss in order to recover the correct erase cycle count.