Erase Gate Doping for NVM Electrical Erasure
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Solution Overview
Problem
Existing non-volatile memory (NVM) technologies, such as single-poly NVMs, are limited to one-time programming due to the inability to effectively erase electric charges from the floating gate, necessitating a solution for multi-time programming capabilities.
Innovation Solution
A non-volatile memory cell structure is developed, featuring a semiconductor substrate with oxide define regions, a floating gate transistor, and an erase gate region, where the erase gate region includes doped regions with higher doping concentrations to facilitate efficient charge erasure through Fowler-Nordheim tunneling, enabling multi-time programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-poly NVM structure with floating gate is used, then the memory can retain information without power, but the electrical erase function fails and UV light exposure is required for erasing
Solution Approach 1:
The gate structure is segmented into two independent gates: a control gate for programming operations and an erase gate for erasing operations. This segmentation allows each gate to be optimized for its specific function, enabling electrical erasure while maintaining the floating gate's charge retention capability.
Solution Approach 2:
A tunnel oxide layer is introduced as an intermediary between the erase gate and the floating gate. This tunnel oxide enables Fowler-Nordheim tunneling, which serves as the mechanism for electrical erasure by allowing charges to be removed from the floating gate through the tunnel barrier when voltage is applied to the erase gate.
2Reliability
If the floating gate is used for storing charges, then the memory achieves non-volatile storage, but the junction breakdown voltage is insufficient for effective charge erasure
Solution Approach 1:
The erase gate region is doped with a doping concentration higher than that of the substrate, creating a localized region with enhanced electrical properties. This local quality change increases the junction breakdown voltage specifically in the erase gate region, enabling effective electrical erasure without affecting the overall floating gate charge storage capability.
3Ease of manufacture
If UV light exposure is used for erasing charges, then the floating gate can be erased, but the memory becomes one-time programmable rather than multi-time programmable
Solution Approach 1:
The optical erasure mechanism (UV light exposure) is replaced with an electrical erasure mechanism using the erase gate and Fowler-Nordheim tunneling. This substitution enables the memory to be erased electrically multiple times, transforming it from one-time programmable to multi-time programmable while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure allows for the electrical erasure of charges from the floating gate, enhancing the memory's cycling times and lifetime by increasing the junction breakdown voltage and programming operations, thus enabling multi-time programmable (MTP) capabilities.
Implementation Method 1
the erase gate region includes doped regions with higher doping concentrations to facilitate efficient charge erasure through Fowler-Nordheim tunneling
Data Source
AI summary
A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.