Erase Management in Non-Volatile Memory Systems
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Solution Overview
Problem
Non-volatile memory systems face performance degradation and increased intrinsic charge loss due to prolonged erase states, leading to reduced read window budgets and premature failure of storage cells, especially when exposed to high temperatures.
Innovation Solution
Implementing a data management system that controls the erase dwell time of storage cells by delaying the erasure of invalid data until closer to the time of reprogramming, thereby reducing the time cells are in an erased state and minimizing intrinsic charge loss and read window budget degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If storage cells are erased immediately when invalid data is detected, then the storage cells become available for subsequent programming quickly, but the storage cells experience prolonged erase states that increase intrinsic charge loss and degrade read window budgets
Solution Approach 1:
The patent applies preliminary action by pre-allocating erase buffers and preparing replacement data before the actual erase operation. The system identifies invalid data blocks, allocates clean buffer blocks in advance, and prepares to erase only when replacement data is ready, thus minimizing the time storage cells spend in the erase state while ensuring they are ready for immediate reuse.
Solution Approach 2:
The patent implements skipping by rapidly transitioning storage cells from the erase state directly to the programmed state using pre-prepared replacement data. The erase operation is completed quickly and the cells are immediately overwritten with valid data, minimizing the dwell time in the vulnerable erase state and reducing intrinsic charge loss.
2Adaptability or versatility
If storage cells remain in the erased state for extended periods, then data can be overwritten at any time, but intrinsic charge loss increases and read window budget degrades
Solution Approach 1:
The patent applies periodic action by implementing a structured erase and overwrite cycle with defined time intervals. The system periodically monitors storage cell states, performs erases only when necessary and for limited durations, and systematically overwrites with replacement data. This periodic management prevents prolonged erase states while maintaining operational flexibility.
Solution Approach 2:
The patent changes the time parameter by implementing a maximum erase dwell time threshold. The system monitors and controls the duration that storage cells remain in the erase state, enforcing a time limit that prevents excessive charge loss. This parameter control allows flexibility in scheduling while constraining the harmful effect of prolonged erasure.
3Reliability
If the erase operation is delayed until replacement data is ready, then the time in erase state is minimized, but the storage cells are not available for other programming operations
Solution Approach 1:
The patent segments the memory system into multiple regions including active data blocks, erase buffers, and replacement data storage. This segmentation allows different operations to proceed in parallel: while one region is being erased, other regions can be programmed or prepared. The segmented architecture eliminates the trade-off by enabling concurrent operations across different memory segments.
Solution Approach 2:
The patent introduces erase buffers as intermediary storage blocks that temporarily hold replacement data before the actual erase operation. These intermediary buffers act as a mediator between the invalid data blocks and the final programmed state, allowing the system to prepare replacement data without forcing an immediate erase, thus minimizing the time storage cells spend in the erase state while maintaining availability.
Data Source
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AI summary
Computer processor hardware receives notification that data stored in a region of storage cells in a non-volatile memory system stores invalid data. In response to the notification, the computer processor hardware marks the region as storing invalid data. The computer processor hardware controls the magnitude of erase dwell time (i.e., the amount of time that one or more cells are set to an erased state) associated with overwriting of the invalid data in the storage cells with replacement data. For example, to re-program respective storage cells, the data manager must erase the storage cells and then program the storage cells with replacement data. The data management logic can control the erase dwell time to be less than a threshold time value to enhance a life of the non-volatile memory system