Multi-Stage Erase Operation for Memory Cell Interference Reduction
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Solution Overview
Problem
Cell-to-cell interference in memory sub-systems increases due to pillar pitch scaling, leading to expanded threshold voltage distributions and reduced read window budget, which affects data reliability and storage efficiency.
Innovation Solution
A multi-stage erase operation is executed, involving alternating wordline erase sub-operations to inject electrons into inter-cell regions of the charge trap layer, reducing cell-to-cell interference by shielding electric fields and minimizing electron injection during subsequent programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pillar pitch is scaled down to increase storage density, then storage capacity is improved, but cell-to-cell interference increases
Solution Approach 1:
The patent applies preliminary action by executing a multi-stage erase operation before programming. Specifically, electrons are injected into inter-cell regions during the erase stage using alternating wordline activation, and then a verify operation checks the threshold voltage distribution. This preliminary preparation reduces cell-to-cell interference before the actual programming operation, enabling tighter pillar pitch scaling while maintaining data reliability.
2Reliability
If multi-stage erase operation is implemented to reduce cell-to-cell interference, then data reliability is improved, but operation complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the erase operation into multiple distinct stages: an initial erase stage that activates alternating wordlines in sequence, an intermediate verify stage that checks threshold voltage distribution, and a final programming stage. This segmentation allows the system to manage complexity through structured, manageable steps rather than a single complex operation, improving data reliability while keeping the operation sequence organized and controllable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-stage erase operation effectively reduces cell-to-cell interference, maintaining data reliability and storage efficiency by minimizing the number of electrons that can be programmed into inter-cell regions, thereby preserving the read window budget.
Implementation Method 1
A multi-stage erase operation is executed, involving alternating wordline erase sub-operations to inject electrons into inter-cell regions of the charge trap layer
Implementation Method 2
reducing cell-to-cell interference by shielding electric fields and minimizing electron injection during subsequent programming operations
Data Source
AI summary
Control logic in a memory device causes a programming pulse to be applied to a set of wordlines, where the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions. The control logic executes a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions. The control logic executes a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.