Two-Phase Erase Speed Adjustment for Non-Volatile Storage Endurance
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in increasing the number of erase/program cycles while efficiently erasing memory cells, as they are prone to over-erasure, which reduces endurance and can lead to uncorrectable errors.
Innovation Solution
Implementing a two-phase erase process where memory cells are initially erased at a faster speed until they pass a first verify level, followed by a second phase at a slower speed until they reach a lower second verify level, thereby preventing over-erasure and enhancing endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single-phase fast erase process is used, then erase speed is improved, but over-erasure occurs reducing memory cell endurance
Solution Approach 1:
The erase operation is divided into two distinct phases: a first phase that erases memory cells at a first speed until they pass a first verify level, and a second phase that erases memory cells at a second speed (slower than the first speed) until they pass a second verify level. This segmentation allows the system to achieve fast initial erasure while preventing over-erasure through the slower second phase, thereby improving both erase speed and memory cell endurance.
2Loss of time
If erase voltage magnitude is increased to speed up erasure, then erase time is reduced, but memory cells are subjected to excessive stress
Solution Approach 1:
The erase operation dynamically adjusts the erase speed between two phases. The first phase operates at a higher speed to quickly reduce erase time, while the second phase transitions to a slower speed to minimize stress on memory cells. This dynamic adjustment of erase parameters allows the system to optimize both erase time and reduce harmful stress effects on the memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the number of program/erase cycles and reduces over-erasure, improving memory cell endurance without significantly increasing erase time.
Implementation Method 1
Erasing the memory cells can be achieved by removing the electrons from the floating gate, thereby lowering the threshold voltage
Implementation Method 2
VPGM is applied to the control gate and the bit line is grounded, causing electrons from the channel of a cell or memory element, e.g., storage element, to be injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory element is raised
Data Source
AI summary
Techniques are disclosed herein for erasing non-volatile storage. The erase has two or more phases. The first phase includes erasing a group of non-volatile storage elements at a first speed until the group of non-volatile storage elements pass a first verify level. The second phase is performed after the group of non-volatile storage elements pass the first verify level. The second phase includes erasing the group of non-volatile storage elements at a second speed that is less than the first speed until the group of non-volatile storage elements pass a second verify level that is lower than the first verify level. Erasing at the first speed results in a fast erase without significant risk of over-erasing the storage elements. Erasing at the second speed during the second phase prevents or reduces over-erasure which could damage the storage elements.