Nonvolatile Memory Erase Transistors Relocation
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Solution Overview
Problem
The existing vertical memory devices face limitations in size reduction due to the peripheral circuits associated with the memory cell array, particularly the page buffers, which hinder further miniaturization efforts.
Innovation Solution
The nonvolatile memory device incorporates erase transistors within the cell region using erase channel structures, eliminating the need for these transistors in the page buffer circuit, thereby reducing the overall size of the page buffer and the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase transistors are included in the page buffer circuit, then the memory device can perform erase operations, but the overall size of the memory device increases
Solution Approach 1:
The erase transistor is extracted from the page buffer circuit and relocated to the cell region. Specifically, the erase transistor is integrated into the contact area adjacent to the memory cell array, where it shares the same region as the bitline and source line connections. This extraction removes the erase transistor from the peripheral circuit area, thereby reducing the overall memory device size while preserving erase functionality.
Solution Approach 2:
The erase transistor is merged with the cell region structures, sharing the same physical space as the bitline and source line connections. The erase transistor's source and drain are integrated with the contact area infrastructure, combining multiple functions (erase operation, bitline connection, source line connection) into a single region rather than having separate dedicated areas for each function.
2Volume of moving object
If vertical memory structures are used to increase integration density, then the memory cell array size is reduced, but the peripheral circuits still occupy significant space limiting further size reduction
Solution Approach 1:
The erase transistor is moved from the two-dimensional peripheral circuit plane into the cell region space. By utilizing the contact area region that is adjacent to and shares infrastructure with the memory cell array, the design effectively adds a spatial dimension for component placement, allowing the erase transistor to occupy space that would otherwise be unused or partially used in traditional layouts.
Solution Approach 2:
The contact area region serves multiple functions: it provides connections for the bitline, source line, and now the erase transistor. This multi-functional use of the same physical region eliminates the need for separate dedicated areas for each function, thereby reducing the total peripheral circuit area while maintaining all necessary operations.
Data Source
AI summary
A nonvolatile memory device includes bitlines, a source line, cell channel structures, a gate electrode structure, erase channel structures and an erase selection line. The bitlines are disposed at a first end portion of a cell region, arranged in a first horizontal direction and extend in a second horizontal direction. The source line is disposed at a second end portion of the cell region and extend in the second horizontal direction. The cell channel structures are disposed in a cell string area of the cell region and are respectively connected between the bitlines and the source line. The erase channel structures are disposed in a contact area of the cell region and respectively connected between the bitlines and the source line. The erase channel structures include erase transistors. The erase selection line is disposed in the contact area to form a gate electrode of the erase transistors.