3D NAND Erase Verification Voltage Segmentation
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Solution Overview
Problem
In three-dimensional non-volatile memory, the existing layered erasure verification method often results in too many memory cells with shallow erase effects due to the uniform application of erasure verification voltage across all layers, which affects the distribution of erased memory cells.
Innovation Solution
The proposed data erasure verification method involves selecting specific layers in a three-dimensional non-volatile memory and applying local verification voltages that are lower than the global verification voltage required for full-block erasure verification, thereby improving the distribution of erased memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a uniform global verification voltage is applied to all layers during layered erasure verification, then the verification process is simplified and can be performed efficiently, but too many memory cells exhibit shallow erase effects and the distribution of erased memory cells deteriorates
Solution Approach 1:
The patent applies different verification voltages to different layers based on their specific characteristics. The controller determines whether each layer is a first layer (with first verification voltage) or second layer (with second verification voltage), creating local quality variations in the verification process to achieve uniform erase depth across all layers while maintaining operational efficiency
Solution Approach 2:
The patent changes the verification voltage parameter from a uniform global voltage to differentiated layer-specific voltages. By adjusting the verification voltage according to layer type (first layer vs. second layer), the system optimizes both the efficiency and precision of the erasure verification process
2Manufacturing precision
If layered erasure verification is performed on each layer independently, then the erasure verification can be optimized for each layer, but the process complexity increases compared to full-block erasure verification
Solution Approach 1:
The patent segments the verification process into distinct layers, treating each layer independently with appropriate verification voltages. This segmentation allows precise control over erase depth for each layer while the controller manages the segmented process systematically to avoid excessive complexity
Solution Approach 2:
Instead of applying a single global verification voltage to all layers (the conventional approach), the patent inverts the approach by applying differentiated verification voltages to different layers. This inversion resolves the contradiction by achieving high precision through layer-specific optimization while the controller manages the complexity
Data Source
AI summary
A method for performing an erase operation of a memory device is disclosed. The memory device includes at least one memory block, and the memory block includes a first deck and a second deck. A first erase operation is performed on the first deck. A first verification voltage is applied to at least one first word line coupled to the first deck to verify the first erase operation for the first deck. A second erase operation is performed on the second deck. A second verification voltage is applied to at least one second word line coupled to the second deck to verify the second erase operation. The second verification voltage is different from the first verification voltage.