Erase Verify Using Inverted Read and P-Well Bias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for verifying the erased state of memory cells in flash memory devices are inefficient due to the difficulty in generating negative voltages, leading to expensive and complex erase verify operations, and result in different timing and voltages compared to read operations, complicating memory cell operations.
Innovation Solution
The solution involves biasing the p-well containing the memory cells with a negative voltage during the erase verify operation, allowing the erase verify to have the same timing as a normal read operation and maintaining a consistent back bias throughout the memory block, enabling efficient and uniform memory cell operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inverted read operation is used for erase verify, then the erase verify operation can be performed without generating negative voltages, but the timing and voltages become very different from normal read operations, increasing operational complexity
Solution Approach 1:
The patent applies inversion by reversing the roles of bit line and source line voltages during erase verify. Instead of applying negative voltage to the bit line as in conventional reads, the patent applies positive voltage to the bit line and uses the source line as the reference, effectively inverting the read operation to perform erase verify without negative voltages while maintaining compatibility with normal read timings
2Measurement precision
If conventional erase verify with negative bit line voltage is used, then the erase threshold can be verified accurately, but the operation becomes expensive and complex due to difficulty in generating negative voltages
Solution Approach 1:
The patent introduces the source line as an intermediary element that mediates between the bit line and the memory cell during erase verify. By using the source line as a voltage reference and applying positive voltage to the bit line, the patent achieves accurate threshold verification without requiring complex negative voltage generation circuitry
3Reliability
If erase verify uses different timing and voltages than read operations, then erase verification can be performed, but memory cell operations become complicated and non-uniform
Solution Approach 1:
The patent makes the read operation circuitry universal by enabling it to perform both normal read operations and erase verify operations using the same timing and voltage sequences. The inverted read operation uses the same bit line and source line roles as conventional reads, allowing a single unified operation sequence to serve multiple functions without requiring separate verify circuits
Data Source
AI summary
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).