Erase Voltage Generator Timing for Uniform Memory Block Erasure
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Solution Overview
Problem
Conventional erase voltage generation circuits in non-volatile semiconductor memory devices face challenges in setting an appropriate erase period, leading to either incomplete erasure of memory cells when the period is short or over-erasure when it is long, due to varying erase execution times based on the number of memory blocks.
Innovation Solution
An erase voltage generation circuit that includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit, and a discharging unit, where the execution time checking unit generates signals to control the high voltage generation and discharge units to ensure a uniform erase execution time by activating the discharge unit once the erase voltage reaches a target level and the execution time has lapsed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the erase period is set short, then the erase execution time is reduced, but non-erased memory cells may exist when the number of memory blocks is large
Solution Approach 1:
The patent introduces a predetermined time period that starts from the activation of the level detection signal. This predetermined time ensures that the erase operation completes uniformly regardless of the number of memory blocks. The high voltage generation unit is disabled and discharge unit is activated after this predetermined time elapses, guaranteeing sufficient erase time for all blocks while maintaining consistent execution time across different erase scenarios.
2Reliability
If the erase period is set long, then the erase execution time is increased, but over-erased memory cells may exist when the number of memory blocks is small
Solution Approach 1:
The patent establishes a predetermined time period that is optimized for the maximum number of memory blocks. This predetermined time is long enough to ensure complete erasure of all blocks but is uniformly applied regardless of the actual number of blocks being erased. The control unit disables the high voltage generation unit and activates the discharge unit after this predetermined time elapses from the level detection signal activation, preventing over-erasure while maintaining consistent execution time.
3Reliability
If the number of memory blocks to be erased is large, then the level rising time increases, but the erase execution time becomes ununiformly long
Solution Approach 1:
The patent introduces a predetermined time period that begins when the level detection signal is activated (when erase voltage reaches target level). This predetermined time is designed to accommodate the maximum level rising time for all memory blocks. By disabling the high voltage generation unit and activating the discharge unit after this predetermined time elapses, the patent ensures uniform erase execution time across different numbers of memory blocks, preventing both incomplete and over-erasure conditions.
Data Source
AI summary
An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.