GIDL Erase Voltage Profiling in 3D Nonvolatile Memory Blocks

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Solution Overview

Problem

The gate-induced drain leakage (GIDL) erase scheme in three-dimensional nonvolatile memory devices leads to the generation of hot carriers, which degrade the on-off characteristics of selection transistors due to channel gradient distortion.

Innovation Solution

The nonvolatile memory device adjusts erase conditions, such as the slope of the erase voltage and the floating time of row lines, based on the number of program/erase cycles to prevent or reduce the generation of hot carriers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If GIDL erase scheme is used to perform erase operation on target block, then erase operation can be completed, but hot carriers are generated which degrade the on-off characteristics of selection transistor

Engineering Contradiction:

Improveerase operation capabilityVSAvoidon-off characteristic of selection transistor

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent changes the slope parameter of the erase voltage based on the number of executed program/erase cycles. By adjusting the voltage slope from steep to gradual, the patent reduces hot carrier generation while maintaining erase functionality, thus resolving the contradiction between erase capability and transistor reliability

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic adjustment of erase conditions (voltage slope and floating time) according to the wear level of the memory block. The control logic dynamically selects different erase schemes based on the number of P/E cycles, making the system adaptive to prevent hot carrier generation as the device ages

Inventive Principle:

Principle #15Dynamics

2Productivity

If steep slope of erase voltage is applied to complete erase operation quickly, then productivity is improved, but channel gradient distortion increases causing hot carrier generation

Engineering Contradiction:

Improveerase speedVSAvoidhot carrier generation

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent directly controls the slope parameter of the erase voltage. By changing the voltage application rate from steep to gradual, it reduces the channel gradient distortion that causes hot carrier generation, while still completing the erase operation within acceptable time frames

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies erase voltage in a controlled, time-dependent manner with different phases. The gradual voltage application can be viewed as a periodic or staged process that avoids sudden voltage spikes, thereby reducing hot carrier generation while maintaining erase effectiveness

Inventive Principle:

Principle #19Periodic action

3Manufacturing precision

If floating time of row line is extended to improve erase uniformity, then erase operation quality is improved, but hot carrier generation increases due to prolonged exposure

Engineering Contradiction:

Improveerase uniformityVSAvoidhot carrier generation

Core Design Contradiction:

Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent dynamically adjusts the floating time parameter of row lines based on the number of executed program/erase cycles. By reducing floating time for worn blocks and compensating with optimized voltage slopes, it maintains erase uniformity while minimizing hot carrier generation exposure time

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic control of floating time according to the wear state of the memory block. The control logic adapts the floating duration to prevent excessive hot carrier generation while ensuring adequate erase uniformity, resolving the contradiction between quality and harmful effects

Inventive Principle:

Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the on-off characteristics of selection transistors and extends the lifetime of the memory device by minimizing channel gradient distortions and hot carrier generation.

Implementation Method 1

a gate induced drain leakage (GIDL) erase scheme is being developed as one of erase schemes for the 3D nonvolatile memory device

Methodology Applied

Scientific EffectGate-induced drain leakage (GIDL):

Implementation Method 2

the GIDL erase scheme may cause reduction of an on-off characteristic of a selection transistor, due to the generation of hot carriers

Methodology Applied

Scientific EffectHot carrier generation:

Data Source

PatentUS12518840B2Nonvolatile memory device supporting GIDL erase operation

Publication Date: 2026.01.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device includes a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.