Erase Voltage Generator Circuit for Uniform Memory Erase Timing
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Solution Overview
Problem
Conventional erase voltage generation circuits in non-volatile semiconductor memory devices face challenges in setting an appropriate erase period, leading to either incomplete erasure of memory cells when the period is short or over-erasure when it is long, due to varying erase execution times based on the number of memory blocks.
Innovation Solution
An erase voltage generation circuit comprising a high voltage generation unit, a voltage level detection unit, an execution time checking unit, and a discharging unit, which generates an execution end signal to disable the high voltage generation and enable discharging after the erase voltage reaches a target level, ensuring uniform erase execution time regardless of the number of memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the erase period is set short, then productivity is improved, but reliability deteriorates because non-erased memory cells may exist when the number of memory blocks is large
Solution Approach 1:
The patent implements a feedback mechanism where the pumping operation is controlled by a fed back level detect signal /XDET from the voltage level detection unit. This feedback loop continuously monitors the erase voltage level and adjusts the pumping operation accordingly, ensuring that the erase operation completes reliably regardless of the number of memory blocks being erased.
Solution Approach 2:
The patent introduces dynamic control of the erase voltage generation process. The high voltage generation unit's pumping operation is dynamically adjusted based on the detected voltage level and the number of memory blocks, allowing the system to adapt the erase period to the actual workload while maintaining reliability.
2Reliability
If the erase period is set long, then reliability is improved, but productivity deteriorates because over-erased memory cells may exist when the number of memory blocks is small
Solution Approach 1:
The feedback mechanism using the level detect signal /XDET prevents over-erasure by stopping the pumping operation exactly when the target voltage level is reached. This ensures that the erase period is extended only as long as necessary, avoiding unnecessary over-erasure operations that would waste time when few memory blocks are being erased.
Solution Approach 2:
The patent applies partial action by performing the pumping operation only to the extent necessary to reach the target voltage level, rather than continuously for a fixed extended period. This prevents excessive erasure operations while ensuring sufficient erasure is achieved.
3Productivity
If the number of memory blocks to be erased increases, then productivity is improved through batch processing, but the level rising time increases causing inconsistent erase execution time
Solution Approach 1:
The patent implements dynamic control where the erase execution time is adjusted based on the number of memory blocks being erased. The control unit receives the number of memory blocks information and dynamically sets the erase execution time parameter, allowing the system to maintain consistent performance characteristics across different batch sizes.
Solution Approach 2:
The patent changes the erase execution time parameter based on the workload size. When more memory blocks are erased, the erase execution time is extended proportionally, maintaining the relationship between processing volume and time required. This parameter adaptation ensures consistent erase execution characteristics regardless of batch size.
Data Source
AI summary
An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.