Erasing Voltage Waveform for Semiconductor Storage Reliability
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Solution Overview
Problem
The reliability of the erasing operation for memory cell transistors in semiconductor storage devices is compromised due to variations in the concentration profile of n-type impurities in the n-type diffusion layer, leading to inconsistent GIDL current generation across memory holes, which affects data erasure reliability.
Innovation Solution
The semiconductor storage device employs an erasing voltage that rises to a first value, falls to a second value, and is maintained at that second value, ensuring consistent GIDL current generation across memory holes by applying the erasing voltage VERA to the source line SL and VERA_GIDL to the source side select line SGS, and adjusting the word line voltages to maintain reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant erasing voltage is applied to the source line, then the erasing operation can be performed, but variations in GIDL current generation occur due to n-type impurity concentration profile variations, reducing erasing reliability
Solution Approach 1:
The patent applies a dynamic erasing voltage waveform instead of a constant voltage. The voltage rises to a first value, falls to a second value, and is maintained at the second value. This dynamic adjustment compensates for variations in GIDL current generation caused by n-type impurity concentration profile variations across different memory holes, thereby improving erasing operation reliability.
Solution Approach 2:
The patent changes the voltage parameter over time during the erasing operation. By adjusting the erasing voltage from a first value to a second value and maintaining it, the patent optimizes the erasing effect across memory holes with different impurity concentrations, ensuring consistent GIDL current generation and improving manufacturing precision of the erasing operation.
2Manufacturing precision
If the erasing voltage is continuously adjusted to compensate for impurity variations, then GIDL current consistency improves, but the voltage application complexity increases
Solution Approach 1:
The patent employs a periodic voltage waveform with specific rise and fall characteristics. The voltage rises to a first value, then falls to a second value, and is maintained. This periodic pattern simplifies the control logic compared to continuous adjustment while achieving consistent GIDL current generation across memory holes with varying impurity concentrations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the erasing operation by reducing variations in GIDL current generation across memory holes, ensuring consistent data erasure even with varying n-type impurity profiles, thereby improving the overall reliability of the semiconductor storage device.
Implementation Method 1
variations in the concentration profile of n-type impurities in the n-type diffusion layer, leading to inconsistent GIDL current generation across memory holes
Data Source
AI summary
A semiconductor storage device includes a plurality of memory cell transistors, a first wiring electrically connected to the plurality of memory cell transistors, and an erasing circuitry. The erasing circuitry is configured to erase data stored in the memory cell transistors by applying a first voltage to the first wiring, and apply the first voltage such that the first voltage rises to a first value, then falls from the first value to a second value, and is then maintained at the second value.