Hardware Accelerator Erasure Coding Bypasses CPU Buffer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing distributed storage systems face inefficiencies in performing erasure coding, as they require significant CPU resources and network traffic due to the need for multiple data transmissions and CPU coordination, which can increase computational load and network traffic.
Innovation Solution
A hardware accelerator with a dedicated buffer memory is used to perform erasure coding operations on write data, allowing direct data receipt from a compute node and direct transmission of parity data to storage devices, bypassing the CPU and reducing data movement and computational load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erasure coding is performed using traditional CPU-based methods in distributed storage systems, then data protection and redundancy are achieved, but CPU resource utilization increases and network traffic increases due to multiple data transmissions and CPU coordination
Solution Approach 1:
The patent extracts the erasure coding computational tasks from the CPU and relocates them to dedicated hardware accelerator devices. This separation allows the CPU to focus on coordination and control functions while the hardware accelerator handles the computationally intensive encoding operations, thereby reducing CPU resource utilization while maintaining data protection capabilities.
Solution Approach 2:
The patent introduces hardware accelerator devices as intermediary components between the storage system and the data. These accelerators serve as specialized mediators that perform erasure coding operations more efficiently than general-purpose CPUs, reducing both computational load on the CPU and the time required for encoding operations.
2Reliability
If erasure coding is performed using traditional CPU-based methods in distributed storage systems, then data protection and redundancy are achieved, but network traffic increases due to multiple data transmissions
Solution Approach 1:
The patent extracts the erasure coding computational tasks from the CPU and relocates them to dedicated hardware accelerator devices. This separation allows the CPU to focus on coordination and control functions while the hardware accelerator handles the computationally intensive encoding operations, thereby reducing CPU resource utilization while maintaining data protection capabilities.
Solution Approach 2:
The patent introduces hardware accelerator devices as intermediary components between the storage system and the data. These accelerators serve as specialized mediators that perform erasure coding operations more efficiently than general-purpose CPUs, reducing both computational load on the CPU and the time required for encoding operations.
3Ease of operation
If data is transmitted through the CPU buffer memory for erasure coding operations, then data processing is performed, but data movement through the storage node increases, reducing efficiency
Solution Approach 1:
The patent extracts the erasure coding computational tasks from the CPU and relocates them to dedicated hardware accelerator devices. This separation allows the CPU to focus on coordination and control functions while the hardware accelerator handles the computationally intensive encoding operations, thereby reducing CPU resource utilization while maintaining data protection capabilities.
Solution Approach 2:
The patent introduces hardware accelerator devices as intermediary components between the storage system and the data. These accelerators serve as specialized mediators that perform erasure coding operations more efficiently than general-purpose CPUs, reducing both computational load on the CPU and the time required for encoding operations.
Data Source
AI summary
A method and a hardware accelerator device are provided for performing erasure coding on the hardware accelerator device that includes a dedicated buffer memory that is resident on the hardware accelerator device and that is connected to a second device via a bus, the method includes receiving, at the dedicated buffer memory, write data directly from the second device via the bus such that receiving the data at the dedicated buffer memory bypasses a buffer memory connected to a central processing unit (CPU), performing, at the hardware accelerator, an erasure coding operation on the write data received at the dedicated buffer memory to generate parity data based on the received write data, transmitting the parity data directly to a storage device connected to the hardware accelerator device via the bus such that transmitting the parity data bypasses the buffer memory connected to the CPU.