Erasure FEC Decoder Two-Dimensional Error Correction

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Solution Overview

Problem

Existing FEC decoding methods, particularly in two-dimensional codes, face limitations in correcting certain error patterns due to the 'decoding BER floor' issue, where some error configurations cannot be corrected by mono-dimensional iterative decoding, and existing erasure methods are complex and prone to false corrections.

Innovation Solution

A novel erasure algorithm and method that divides into an errored cell detection step and a correction step, allowing for the identification and correction of error patterns without solving complex linear systems, using a combination of full and reduced-capacity decodings along dimensions to accurately detect and correct errors, while minimizing false corrections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If mono-dimensional iterative decoding is used, then the decoding process is simple and fast, but certain error patterns cannot be corrected (decoding BER floor)

Engineering Contradiction:
Improvedecoding process simplicityVSAvoiderror correction capability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent transitions from mono-dimensional iterative decoding to two-dimensional decoding by adding a spatial dimension to the decoding process. The data is arranged in a two-dimensional array and decoded along both horizontal and vertical dimensions, allowing the decoder to exploit redundancy in both directions simultaneously. This dimensional expansion enables correction of error patterns that are uncorrectable by single-dimensional methods, thereby resolving the BER floor issue while maintaining operational simplicity through systematic algorithms.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If erasure methods are used to correct error patterns, then more error patterns can be corrected, but the method becomes complex and prone to false corrections

Engineering Contradiction:
Improveerror correction capabilityVSAvoidalgorithm complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the error correction process into distinct phases: first identifying error locations through syndrome calculation and location polynomial computation, then determining error values separately. This segmentation allows the complex erasure correction problem to be broken down into manageable sub-tasks, reducing overall algorithmic complexity and minimizing the risk of false corrections by handling location and value determination independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate mathematical structures (syndromes, location polynomials, and value polynomials) that serve as mediators between the received data and the final corrected output. These intermediaries simplify the correction process by transforming the complex error detection and correction problem into a series of algebraic operations, making the algorithm more systematic and less prone to errors while maintaining high correction capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If full capacity decoding is performed in both dimensions, then all error patterns can be corrected, but the processing time and computational load increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing full-capacity decoding only when necessary (when syndromes indicate errors) rather than always executing complete two-dimensional decoding. The algorithm first performs quick syndrome checks and only initiates the full correction process when errors are detected, thereby reducing average processing time while maintaining the capability to correct all error patterns within capacity when they occur.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS7346826B2Erasure FEC decoder and method
Publication Date: 2008.03.18 WSOU INVESTMENTS LLC
  • US7346826B2 patent drawing
  • US7346826B2 patent drawing
  • US7346826B2 patent drawing

AI summary

Disclosed is a method and erasure FEC decoder for correcting a pattern of errors by a two-dimensional decoding, the pattern of errors comprising at least two codewords in both a first and a second dimensions with a number of errors in common higher than the capacity of the code which is used for decoding. The method comprises the steps of: performing a full capacity decoding along the second dimension for removing possible false corrections introduced by a previous decoding performed along the first dimension; performing a reduced-capacity decoding along the first dimension, for identifying errored codewords along the first dimension; performing a full capacity decoding along the second dimension with disabled correction feature for identifying errored codewords along the second dimension; detecting the error coordinates from the information from steps b) and c); and correcting the detected pattern of errors.