Semi-Static Error Bank Architecture for Multi-Event RAS Logging

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Solution Overview

Problem

Existing RAS specifications limit error logging to static allocation, preventing the recording of multiple errors associated with the same hardware structure, leading to information loss.

Innovation Solution

Implementing a semi-static storage allocation method that dynamically logs error events in a dynamic storage area while maintaining static storage for error records, linking them through an association based on hardware structure, allowing multiple error entries for a single component.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If static allocation is used for error logging, then compliance with RAS technical specifications is maintained, but multiple errors associated with the same hardware structure cannot be recorded

Engineering Contradiction:
Improvecompliance with RAS specificationsVSAvoiderror event information
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The error bank is divided into two distinct storage areas: a static storage area for maintaining RAS specification compliance and a dynamic storage area for capturing multiple error events. This segmentation allows each area to serve its specific function without compromising the other, resolving the contradiction between specification compliance and comprehensive error recording.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A linkage mechanism acts as an intermediary between the static and dynamic storage areas, connecting error records in static storage with their corresponding error events in dynamic storage. This intermediary structure enables the system to maintain static allocation compliance while simultaneously capturing multiple errors through the dynamic area.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If static allocation is used for error logging, then storage structure is simple, but multiple error entries for the same hardware structure are lost

Engineering Contradiction:
Improvestorage allocation structureVSAvoidmultiple error events
Core Design Contradiction:
Device complexityVSLoss of information

Solution Approach 1:

The storage allocation structure is segmented into static and dynamic areas, each serving a specific purpose. The static area maintains simplicity for specification compliance, while the dynamic area provides the flexibility to capture multiple error events, thereby resolving the contradiction between structural simplicity and information completeness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from a single-dimensional static allocation to a two-dimensional structure with static and dynamic storage areas. This dimensional change enables the system to simultaneously maintain static allocation compliance and capture multiple error events that would otherwise be lost in a purely static structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of information

If dynamic storage allocation is implemented, then multiple error events can be logged, but storage management complexity increases

Engineering Contradiction:
Improveerror event captureVSAvoidstorage allocation management
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

By segmenting the storage into dedicated static and dynamic areas, the complexity of storage management is contained within the dynamic area only, while the static area provides a stable foundation for specification-compliant error records. This segmentation isolates the management complexity to a manageable portion of the system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The linkage mechanism serves as an intermediary that simplifies storage management by automatically associating error events with their corresponding records. This intermediary structure reduces the manual management overhead of tracking multiple error events across different storage locations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260072775A1Semi-static error bank architecture in integrated circuits
Publication Date: 2026.03.12 SIFIVE INC
  • US20260072775A1 patent drawing
  • US20260072775A1 patent drawing
  • US20260072775A1 patent drawing

AI summary

The present application relates to devices and components including apparatus, systems, and methods for measurements for serving cell configuration.