Hardware Logic for Error-Bounded Multiplication by Invariant Rationals
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Solution Overview
Problem
Division operations in hardware implementation are expensive and require significant resources, especially when accurate results are not necessary, as they often involve complex logic and large circuit areas.
Innovation Solution
A method to generate a hardware logic representation for multiplication by an invariant rational, which truncates an infinite summation array and converts the binary representation into canonical signed digit notation to reduce the array size while satisfying a defined error bound, allowing for efficient implementation of lossy constant division operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If division operations are implemented in hardware, then accurate calculation capability is achieved, but hardware area and complexity increase significantly
Solution Approach 1:
The patent applies partial action by implementing only the necessary number of summands in the summation array to achieve the required error bound, rather than computing the complete infinite series. This allows the hardware to perform division with controlled accuracy while significantly reducing the number of adders and logic elements needed, thus decreasing hardware area while maintaining acceptable precision.
Solution Approach 2:
The patent changes the parameter of precision by introducing an error bound criterion that determines when the infinite summation can be truncated. By parameterizing the accuracy requirement (εmax), the design can adjust the hardware resources accordingly - higher precision requirements lead to more summands, while lower requirements allow for significant area reduction. This creates a scalable solution that adapts to different application needs.
2Measurement precision
If infinite summation array is used for multiplication by invariant rational, then calculation accuracy is improved, but hardware complexity and area increase
Solution Approach 1:
The patent implements partial action by truncating the infinite summation array after a finite number of summands that satisfy the error bound. This partial implementation dramatically reduces hardware complexity by eliminating the need for infinite logic stages, while still achieving the required accuracy through careful selection of the truncation point based on the error bound criterion.
Solution Approach 2:
The patent segments the infinite summation into a finite number of meaningful terms that contribute significantly to the result, followed by discarded terms that contribute negligibly. This segmentation allows the hardware to focus resources on the critical summands while ignoring the tail end of the series, thereby reducing complexity without sacrificing essential accuracy.
3Area of stationary object
If lossy constant division is implemented, then hardware area is reduced, but calculation error increases
Solution Approach 1:
The patent introduces feedback through the error bound criterion that guides the truncation decision. By continuously evaluating whether adding the next summand would significantly reduce the error below the threshold, the system optimizes the balance between area and precision. The error bound acts as a feedback mechanism that determines the optimal point to stop adding summands, ensuring minimal hardware area while maintaining acceptable accuracy.
Solution Approach 2:
The patent changes the precision parameter by accepting a controlled amount of error (lossy computation) in exchange for reduced hardware area. The error bound εmax serves as a configurable parameter that allows designers to trade off between area and precision according to application requirements, creating a scalable family of implementations from high-precision/high-area to low-precision/low-area solutions.
Data Source
AI summary
A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.