Error Cache for Memory Cell Defect Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory devices are limited in their ability to correct errors beyond a certain threshold, as error checking techniques can only detect and correct up to a specific number of errors, leading to failures when data includes errors beyond this limit.
Innovation Solution
The implementation of an error cache that stores locations of defective memory cells, allowing the memory device to invert bits associated with these cells to correct errors, thereby increasing the number of correctable errors using parity information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error checking techniques are used, then the error correction capability is limited to a specific threshold, but the device complexity remains low
Solution Approach 1:
The patent applies preliminary action by pre-storing error location information in an error cache before actual data reading occurs. When errors are detected during data retrieval, the cached location information enables immediate correction without complex real-time analysis, thereby enhancing reliability while maintaining relatively simple device architecture
Solution Approach 2:
The error cache serves as an intermediary component that stores pre-identified error locations. This intermediary structure mediates between the memory array and the error correction logic, allowing the system to correct multiple errors efficiently by referencing the cached location data rather than implementing complex real-time error detection and correction algorithms
Data Source
AI summary
Methods, systems, and devices for error caching techniques for improved error correction in a memory device are described. An apparatus, such as a memory device, may use an error cache to store indications of memory cells identified as defective and may augment an error correction procedure using the stored indications. If one or more errors are detected in data read from the memory array, the apparatus may check the error cache, and if a bit of the data is indicated as being associated with a defective cell, the bit may be inverted. After such inversion, the data may be checked for errors again. If the inversion corrects an error, the resulting data may be error-free or may include a reduced quantity of errors that may be correctable using an error correction scheme.