Error Cache for Storage Device Hard Error Correction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing data processing systems face challenges in efficiently handling errors in storage devices, particularly hard errors that occur during operation, leading to potential system lock-ups and inefficiencies in error correction mechanisms.

Innovation Solution

A data processing apparatus with an error cache that dynamically replaces erroneous data values with corrected ones, allowing read access requests to be re-routed through the cache instead of the faulty storage device, thereby preventing system lock-ups and ensuring correct operation even with hard errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction is performed by rewriting corrected data back to the storage device, then soft errors can be corrected, but hard errors cannot be corrected and cause system lock-ups

Engineering Contradiction:
Improveerror correction capabilityVSAvoidsystem operation continuity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent introduces a cache memory as an intermediary between the storage device and the processor. When a hard error is detected in the storage device, the corrected data is stored in the cache memory instead of being rewritten to the faulty storage location. The cache then serves as a mediator, providing the correct data to the processor without requiring repeated access to the faulty storage device, thus preventing system lock-ups while maintaining error correction capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the data storage system into two parts: the main storage device and a smaller cache memory. This segmentation allows the system to handle errors differently depending on the storage location - soft errors in the cache can be corrected by rewriting to cache, while hard errors in the storage device are handled by using the cache as a replacement, thus solving the contradiction between correction capability and operational continuity

Inventive Principle:
Principle #1Segmentation

2Reliability

If error detection and correction operations are performed on every read access, then errors can be detected and corrected, but timing and power consumption are adversely affected

Engineering Contradiction:
Improveerror detection capabilityVSAvoidread access timing
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs error detection and correction operations in advance during the cache refill process, rather than on every read access. When data is loaded from the storage device into the cache, error detection and correction are performed preliminarily. This allows subsequent read accesses from the cache to proceed without additional error checking overhead, thus maintaining high reliability while preserving timing performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuous error protection by ensuring that the cache, which is frequently accessed, contains corrected data. The error correction operation is performed continuously during cache maintenance operations, ensuring that the useful action of error detection is maintained without interrupting the continuous flow of data access from the cache

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If a repair cache is populated at production time, then hard errors detected at production can be handled, but hard errors occurring after production and soft errors cannot be handled

Engineering Contradiction:
Improvehard error handling capabilityVSAvoidpost-production error handling
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent makes the error handling system dynamic by implementing error detection and correction operations that run continuously during normal operation, rather than being static as in production-time repair caches. The system can dynamically detect and correct hard errors occurring after production, as well as handle soft errors, by performing error checks on data when it is accessed or loaded into the cache, thus providing adaptability to various error conditions that arise during the device's operational life

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8190973B2Apparatus and method for error correction of data values in a storage device
Publication Date: 2012.05.29 ARM LTD
  • US8190973B2 patent drawing
  • US8190973B2 patent drawing
  • US8190973B2 patent drawing

AI summary

A data processing apparatus is provided in which a processing unit, by means of a read access request, accesses a storage device which stores data values and error data associated with those data values. When the processing unit accesses a data value in the storage device, error detection circuitry detects if an error is present in that data value and, if necessary, error correction circuitry corrects the read data value. An error cache having at least one entry stores corrected replacement data values, a corrected data value being allocated into an entry of the error cache for every corrected data value that is generated, and the read access request is re-performed. Replacement data values are read from the error cache in preference to data values stored in the storage device. This ensures that the retry mechanism will succeed irrespective of whether the error was a soft error or a hard error. Thus, if any hard errors do occur during normal operation of the storage device, they can effectively be temporarily corrected through use of the error cache to ensure that the retry mechanism proceeds correctly.