Error Check-Only Mode for Video Display Pipes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing video systems face challenges in efficiently performing error checking without affecting system performance, particularly in scenarios where a display is not supported or available, and require extensive testing simulations.
Innovation Solution
Incorporating an error-checking block, such as a CRC block, that can operate independently of the display controller, allowing for error checking at the pixel generation rate and enabling/disabling the FIFO buffer to manage pixel processing and storage, thereby facilitating testing without a display connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error checking is performed using a FIFO buffer and display controller, then data accuracy is ensured, but test duration increases and system performance is affected
Solution Approach 1:
The error checking function is segmented from the main display pipeline into a separate ECO mode pathway. The display pipe can operate independently in ECO mode to perform error checking without being constrained by FIFO buffer operations or display controller timing, thus reducing test duration while maintaining data accuracy through dedicated error checking blocks.
Solution Approach 2:
Error checking is performed preliminarily at the pixel generation rate before data would normally be transferred through the FIFO buffer and display controller. By implementing error checking blocks that operate concurrently with pixel generation in ECO mode, the system validates data integrity earlier in the pipeline, reducing the need for extended testing while ensuring accuracy.
2Reliability
If a display controller and display connection are used for testing, then complete system validation is achieved, but device complexity and testing requirements increase
Solution Approach 1:
The error checking functionality is extracted from the display controller pathway into a standalone ECO mode. This allows error checking to be performed independently without requiring a display controller or display connection, simplifying the testing requirements while maintaining system validation through dedicated error checking blocks that operate directly on pixel data from the display pipe.
Solution Approach 2:
The display pipe is designed with multi-functionality to support both normal display operation and ECO mode error checking. By integrating error checking blocks that can operate in both modes, the system achieves universal functionality that validates data accuracy without requiring external display hardware, thereby reducing device complexity for testing purposes.
3Productivity
If pixels are written to FIFO buffer at high rate, then processing speed is maintained, but buffer overflow risk increases and error checking becomes constrained
Solution Approach 1:
The system dynamically switches between normal mode (using FIFO buffer for display output) and ECO mode (bypassing FIFO for direct error checking). In ECO mode, the display pipe maintains high processing speed by writing pixels directly to error checking blocks without FIFO buffer constraints, while the ability to switch modes ensures reliability by allowing error checking to operate independently of buffer status.
Solution Approach 2:
Error checking blocks serve as intermediaries between the display pipe and the FIFO buffer system. In ECO mode, these intermediaries receive pixels directly from the display pipe at full processing speed and perform error checking without being constrained by FIFO buffer write rates or overflow conditions, thus maintaining both productivity and reliability.
Data Source
AI summary
Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available. The results generated by the error-checking may be read and compared to an expected value to detect test pass/fail conditions.