Error Code Generation Circuitry for Redundant Instruction Checking
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Solution Overview
Problem
Existing data processing systems face inefficiencies in checking output data during redundant execution of instructions due to the need to maintain significant output information from the main processor until corresponding output from the redundant processor is available, which increases area and energy consumption.
Innovation Solution
An apparatus and method utilizing error code generation circuitry to generate an error code from the first processing circuit's output data, which is then used for error checking on the redundant output data, allowing for an implicit comparison without directly buffering the first output data, thus reducing the need for extensive buffering and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If output data from the main processor is buffered until redundant processor output is available, then error detection capability is improved, but area and energy consumption increase
Solution Approach 1:
The patent extracts only the essential error-checking information (error codes) from the full output data, rather than buffering the entire output. The error code generation circuitry computes condensed error codes from main processor outputs, and these compact codes are buffered instead of the complete data sets, dramatically reducing the buffering area required while maintaining error detection capability.
Solution Approach 2:
The patent transforms the output data from its original full-form representation into a condensed error code representation. This parameter transformation reduces the data volume significantly, allowing the buffered information to occupy much less area while still containing all necessary error detection information.
2Reliability
If output data from the main processor is buffered until redundant processor output is available, then error detection capability is improved, but energy consumption increases
Solution Approach 1:
The patent extracts only the essential error-checking information (error codes) from the full output data, rather than buffering the entire output. The error code generation circuitry computes condensed error codes from main processor outputs, and these compact codes are buffered instead of the complete data sets, dramatically reducing the buffering area required while maintaining error detection capability.
Solution Approach 2:
The patent transforms the output data from its original full-form representation into a condensed error code representation. This parameter transformation reduces the data volume significantly, allowing the buffered information to occupy much less area while still containing all necessary error detection information.
3Reliability
If redundant processor execution is delayed relative to main processor, then common-cause faults are eliminated, but comparison timing complexity increases
Solution Approach 1:
The patent creates a simplified copy of the comparison function by using error codes instead of full data sets. The error checking circuitry performs comparison based on these condensed codes, which are much simpler to manage and compare than the original full-width data, reducing the timing and control complexity despite the execution delay.
Data Source
AI summary
An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.