Unidirectional Error-Code Transfer for High-Speed Memory Links
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Solution Overview
Problem
Existing memory systems face challenges in maintaining low bit-error-rate (BER) communication due to increased noise and bandwidth limitations, making it difficult to develop faster interfaces with reliability, especially as data rates increase, and conventional interfaces struggle to accommodate higher data rates without significant cost and complexity increases.
Innovation Solution
The implementation of a controller and device system that uses bidirectional data links with dynamic error-detection and correction mechanisms, including encoders, transmitters, receivers, and error-detection logic to compare error-detection information and initiate retry actions, thereby reducing BER and enabling higher bandwidth at lower costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate is increased to achieve faster interfaces, then productivity is improved, but bit-error-rate increases due to increased noise and bandwidth limitations
Solution Approach 1:
The patent applies preliminary action by generating error-detection codes before data transmission and preparing retry mechanisms in advance. The encoder generates error-detection information for each data packet before transmission, and the system prepares retry logic beforehand to handle potential errors, allowing faster data rates without compromising reliability.
Solution Approach 2:
The patent implements feedback through error-detection logic that compares transmitted data with received data using error-detection codes. When errors are detected, the system provides feedback by initiating retry sequences to retransmit affected data packets, thereby maintaining low bit-error-rate even at higher data rates.
2Reliability
If error-detection and correction mechanisms are added to maintain low BER, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing error-detection functionality into separate encoder and error-detection logic components, and splitting data transmission into discrete packets with individual error-detection codes. This modular approach allows error-detection mechanisms to be integrated without proportionally increasing overall system complexity.
Solution Approach 2:
The patent uses error-detection codes as intermediaries between transmitted data and received data. These codes act as a mediator that enables error detection without requiring complex direct comparison of entire data packets, simplifying the error-detection process while maintaining reliability.
3Reliability
If retry mechanisms are implemented to correct errors, then reliability is improved, but loss of time increases due to retransmission
Solution Approach 1:
The patent applies preliminary action by preparing retry sequences in advance and using error-detection codes to quickly identify errors. This allows the system to initiate retries immediately upon error detection without extensive processing delays, minimizing time loss while ensuring data accuracy.
Solution Approach 2:
The patent implements skipping by rapidly progressing through error-detection and retry processes. The error-detection logic quickly identifies erroneous packets, and the system rushes through retransmission of only affected packets rather than retransmitting entire data sequences, thereby reducing time loss while maintaining reliability.
Data Source
AI summary
A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.