Error Code Pattern Generation Circuit for Semiconductor Memory

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Solution Overview

Problem

Conventional semiconductor memory devices face challenges in data transfer speed, leading to increased error probabilities, as external testing devices often cannot keep up with the high operational speed of error code generation circuits, resulting in incomplete recognition of error codes.

Innovation Solution

An error code pattern generation circuit that includes first and second storage units to output error data at different time periods, allowing for error code output in various patterns, particularly in a conversion mode that widens the output window, enabling recognition by lower-frequency test devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the error code generation circuit operates at high frequency to match fast data transfer speeds, then productivity is improved, but the external test device cannot keep up with the output speed, resulting in incomplete error code recognition

Engineering Contradiction:

Improveerror code generation speedVSAvoiderror code recognition completeness

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The error code output is divided into multiple segments corresponding to different data bus widths (e.g., 64-bit, 32-bit, 16-bit segments). Each segment is output in a separate time period, allowing test devices with lower frequency capabilities to capture complete error code information by selecting appropriate segment widths, while high-frequency operation is maintained for data transfer.

Inventive Principle:

Principle #1Segmentation

2Productivity

If the error code is output in a single time period at high speed, then productivity is improved, but external devices operating at lower frequencies cannot capture the complete error code

Engineering Contradiction:

Improvedata transfer speedVSAvoidcompatibility with test devices

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The circuit dynamically adjusts the output timing and segmentation of error codes based on the operational mode and data bus width. Multiple output time periods are generated, each tailored to different bus widths, enabling the system to adapt to various test device capabilities while maintaining high-speed operation for actual data transfer.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The error code output circuit is designed to support multiple output modes simultaneously, accommodating different data bus widths (64-bit, 32-bit, 16-bit, etc.) and frequency requirements. This multi-functional design allows a single circuit to serve both high-speed data transfer operations and compatibility with legacy or lower-frequency test equipment.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If the error code is output all at once, then the output window is narrow and productivity is improved, but low-frequency test devices cannot verify the complete error code

Engineering Contradiction:

Improveerror code output efficiencyVSAvoiderror code output time window

Core Design Contradiction:

ProductivityVSDuration of action of moving object

Solution Approach 1:

The error code output is structured as periodic actions across multiple time periods, with each period corresponding to a specific data bus width segment. This periodic segmentation extends the total output duration while maintaining efficient throughput, allowing test devices to capture complete error codes by observing the appropriate number of periods based on their frequency capabilities.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8612841B2Error code pattern generation circuit and semiconductor memory device including the same

Publication Date: 2013.12.17 SK HYNIX INC

AI summary

An error code pattern generation circuit includes a first storage unit configured to store at least one bit of an error code, and output error data for a first time period; and a second storage unit configured to store at least one remaining bit of the error code and output the error data for a second time period which is different from the first time period.