Error Coding Circuit With Data Rearrangement for Burst Errors
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Solution Overview
Problem
Existing data transmission systems face challenges in efficiently detecting and correcting various types of errors, particularly in high-speed data transmission where conventional error detection and correction methods are inadequate for dynamic error patterns in DRAM systems.
Innovation Solution
A circuit that creates an error coding data block using a combination of data arrangement alteration and error coding algorithms, allowing for flexible selection of error coding paths and algorithms based on a control indicator to optimize error detection and correction for different types of errors, such as temporal and spatial burst errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection and correction methods are used, then implementation is simple, but they are inadequate for dynamic error patterns in high-speed DRAM systems
Solution Approach 1:
The patent implements dynamic error coding by switching between different error coding algorithms (first and second algorithms) based on detected error patterns. The system adapts to temporal and spatial burst errors by selecting appropriate coding algorithms in real-time, making the error detection and correction mechanism dynamic rather than static.
Solution Approach 2:
The patent changes parameters of the error coding process by using different coding algorithms with different characteristics. The first error coding algorithm may use one set of parameters while the second uses different parameters, allowing optimization for different error types (temporal vs spatial burst errors) without changing the hardware architecture.
2Reliability
If multiple error coding algorithms are implemented to handle different error types, then error detection and correction efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the error coding functionality into separate first and second error coding paths, each implementing a different error coding algorithm. This segmentation allows the system to handle different error types through dedicated paths while maintaining modularity. The segmentation is controlled by selection logic that routes data through the appropriate path based on error pattern detection.
3Reliability
If data arrangement alteration is applied to optimize error coding, then error detection capability improves, but processing time increases
Solution Approach 1:
The patent applies data arrangement alteration as a preliminary action before error coding. By pre-organizing data in optimal arrangements (such as interleaving or specific patterns), the system prepares data to maximize error detection capability of subsequent coding operations. This preliminary organization reduces the computational burden during actual error coding, offsetting the initial processing time investment.
Data Source
AI summary
A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to create the error coding data block in accordance with a second error coding; the error coding data block for the first data block being created optionally by the first or second error coding paths, as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.