Error Correction Encoding with Segmented Soft-Decision Bit Protection

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Solution Overview

Problem

Conventional soft decision error correction encoding processes protect all bits except the most significant bit, leading to increased computational requirements as the number of bits to be protected increases.

Innovation Solution

An error correction encoding device that generates soft decision error correction frame information by combining first and second bit string group information, using specific symbol mapping rules to reduce the number of bits protected by soft decision error correction, thereby reducing computational load.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all bits except the most significant bit are protected by soft decision error correction, then error correction capability is improved, but computational load increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcomputational load
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the bit string into multiple groups (first bit string group, second bit string group, third bit string group) with different error correction strategies. The first group uses soft decision error correction while the second and third groups use hard decision error correction, thereby reducing overall computational load while maintaining error correction capability for critical bits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different error correction methods to different portions of the data based on their importance. Specifically, the most significant bit and least significant bit groups receive soft decision error correction for higher reliability, while the middle bit group uses hard decision error correction to reduce computational complexity, achieving local optimization of the error correction strategy.

Inventive Principle:
Principle #3Local quality

2Reliability

If the number of bits protected by soft decision error correction increases, then error correction performance is improved, but processing time increases

Engineering Contradiction:
Improveerror correction performanceVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the bit string into multiple segments and applies soft decision error correction only to specific segments (first and third bit string groups) rather than all bits. This segmentation reduces the total number of bits requiring computationally intensive soft decision processing, thereby reducing processing time while maintaining error correction performance for critical segments.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies soft decision error correction partially rather than universally - specifically to the first and third bit string groups containing the most and least significant bits, while using hard decision error correction for the second bit string group. This partial application of soft decision error correction reduces processing time while still providing adequate error correction performance for the most critical bits.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP4084339B1Error correction encoding device, error correction encoding method, error correction device, error correction method, communication method, and optical communication system
Publication Date: 2024.05.22 MITSUBISHI ELECTRIC CORP
  • EP4084339B1 patent drawingFigure 1
  • EP4084339B1 patent drawingFigure 2
  • EP4084339B1 patent drawingFigure 3

AI summary

An error correction encoding device (100) includes an encoding unit (120) to generate soft decision error correction frame information including a bit array of m rows and N columns obtained by combining first bit string group information and second bit string group information, the first bit string group information including a bit array of m rows and N1 columns in which it is enabled to perform pulse amplitude modulation of a combination of bit values of each column of the first bit string group information into a modulation symbol by using a first symbol mapping rule, the second bit string group information including a bit array of m rows and N2 columns in which it is enabled to perform pulse amplitude modulation of a combination of bit values of each column of the second bit string group information into a modulation symbol by using a second symbol mapping rule.