Error Correction Block Length Control for Image Transmission Delay
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Solution Overview
Problem
High-quality motion picture data transmission over general circuits like Ethernet or wireless networks often results in significant delay, which can corrupt or degrade the real-time display of motion pictures due to large data sizes and unreliable network conditions.
Innovation Solution
An information processing apparatus that estimates the reception buffer waiting time based on the transmission buffer waiting time and sets an error correction block length to ensure the error correction reception delay does not exceed the estimated reception buffer waiting time, inserting parity for error correction to minimize overall delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high quality motion picture data are transmitted via generally-available circuits, then image quality is improved, but delay time increases and real-time property is degraded
Solution Approach 1:
The patent divides the transmission process into segments by introducing error correction codes (parity data) at specific intervals. The encoded data is divided into information data and parity data, where parity data serves as error correction information. This segmentation allows the receiver to reconstruct lost data without requiring retransmission, thereby reducing overall delay time while maintaining high image quality.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and attaching error correction parity data to the encoded motion picture data before transmission. This preliminary error correction preparation ensures that even if data loss occurs during transmission over unreliable networks, the receiver can immediately reconstruct the original data without waiting for retransmission, thus reducing delay time while preserving image quality.
2Reliability
If error correction processing is performed with larger block length, then error correction capability is improved, but error correction reception delay time increases
Solution Approach 1:
The patent applies dynamics by making the block length configurable and adaptable. The system allows the block length to be adjusted based on network conditions and requirements. By dynamically setting the block length, the system can optimize between error correction capability and processing speed, preventing excessive delay while maintaining sufficient error correction capability for reliable transmission.
Data Source
AI summary
The present technique relates to an information processing apparatus and a method, and a program, capable of reducing a delay time. An information processing apparatus according to the present technique is an information processing apparatus including an estimation unit configured to estimate, on the basis of a transmission buffer waiting time which is a time it takes to accumulate encoded data obtained by encoding image data when encoding the image data which are to be transmitted, a reception buffer waiting time which is a time it takes to accumulate the encoded data before the encoded data are decoded at a transmission destination of the encoded data, and a setting unit configured to set a block length which is a processing unit of error correction processing in such a manner that an error correction reception delay time which is a delay time in the error correction processing performed at the transmission destination of the encoded data does not become more than the reception buffer waiting time estimated by the estimation unit. The present technique can be applied to, for example, an information processing apparatus.