Error Correction Circuit for Clock Margin Compensation
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Solution Overview
Problem
As memory devices become more integrated and complex, and interface transfer speeds between chiplets increase, there is a growing need to reduce sampling timing errors of reference clocks provided externally, which existing technologies have not adequately addressed.
Innovation Solution
The development of an error correction circuit that includes a clock delay circuit, an error detection circuit, and a control circuit. This circuit receives an input clock, delays it as needed, and outputs either the original or delayed clock based on a select signal adjusted by the control circuit to correct margin errors detected between output data and latch data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interface transfer speed between chiplets is increased, then the productivity is improved, but the sampling timing error of the reference clock increases
Solution Approach 1:
The patent changes the timing parameter of the clock signal by introducing a delayed clock signal with adjusted phase timing. The clock delay circuit delays the reference clock by a controllable time period to align the sampling timing with the data transmission timing, thereby reducing sampling timing errors while maintaining high transfer speeds.
Solution Approach 2:
The patent introduces a clock delay circuit as an intermediary component between the reference clock source and the sampling circuit. This intermediary delays the clock signal to achieve proper timing alignment without affecting the original reference clock frequency or the data transmission speed.
2Measurement precision
If a clock delay circuit is added to correct timing errors, then the sampling timing accuracy is improved, but the device complexity increases
Solution Approach 1:
The clock delay circuit is designed to perform multiple functions: it delays the reference clock signal, generates phase-aligned clock signals for sampling, and works with the error detection circuit to maintain timing accuracy. This multi-functionality reduces the need for separate timing correction circuits.
Solution Approach 2:
The system uses its own existing resources (the reference clock signal itself) to generate the delayed clock signal needed for timing correction. The clock delay circuit processes the reference clock that is already present in the system, rather than requiring an entirely separate timing reference source.
3Reliability
If the clock delay is adjusted to compensate for margin errors, then the reliability is improved, but the control complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the error detection circuit monitors timing margins and provides information to the control circuit. The control circuit then adjusts the clock delay accordingly to maintain optimal timing margins, creating a closed-loop system that automatically compensates for timing variations.
Solution Approach 2:
The clock delay amount is made dynamic and adjustable rather than fixed. The control circuit can modify the delay time period based on detected timing errors, allowing the system to adapt to varying operating conditions and maintain reliability across different scenarios.
Data Source
AI summary
An error correction circuit includes a clock delay circuit configured to receive an input clock, delay the input clock by a desired time period to generate a delayed clock, and output one of the input clock and the delayed clock as an output clock in response to a select signal, an error detection circuit configured to, receive the output clock and input data, generate output data and latch data based on the output clock and the input data, and detect a margin error based on the output data and the latch data, and a control circuit configured to correct the detected margin error, the correcting the margin error including adjusting a level of the select signal based on whether the margin error has been detected.