Error Correction Apparatus Reducing DRAM Row Switching
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Solution Overview
Problem
Conventional DVD error correction devices experience inefficiencies due to frequent change row operations in dynamic random access memory (DRAM) during outer-code parity decoding, leading to high memory clock consumption and reduced memory utilization efficiency.
Innovation Solution
An error correction device and method that includes a decoding unit, an error buffer, and an error classifying unit to temporarily store and classify error values and addresses, allowing for error correction within subclasses that correspond to the same memory row, thereby minimizing the need for change row operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PO decoding operation is performed on data distributed among multiple DRAM rows, then error correction capability is improved, but frequent change row operations increase memory clock consumption and reduce memory efficiency
Solution Approach 1:
The patent segments the PO decoding process into multiple batches, where each batch processes error addresses belonging to the same DRAM row. The error correction device divides the plurality of error addresses into first error addresses corresponding to a first row and second error addresses corresponding to a second row, performing corrections in sequential batches rather than random access across all rows simultaneously.
Solution Approach 2:
The patent performs preliminary classification of error addresses by their corresponding DRAM row before executing the correction operations. The controller identifies and groups error addresses by row in advance, so that when correction operations are executed, the memory is already positioned at the correct row, eliminating the need for frequent change row operations during the actual correction process.
2Reliability
If PO decoding operation accesses data across multiple DRAM rows, then complete error correction is achieved, but change row operations increase processing time and reduce productivity
Solution Approach 1:
The patent segments the error correction process into row-specific batches, where each batch handles only the error addresses corresponding to a single DRAM row. This segmentation allows the memory controller to process one row at a time, maintaining complete error correction capability while significantly reducing the overhead of frequent row switching operations.
Solution Approach 2:
The patent ensures continuous useful action by organizing the correction operations to process all error addresses within a single row contiguously before moving to the next row. This eliminates idle time and unnecessary row switching during the correction process, as the memory remains in the active state for each row throughout the entire batch of corrections for that row.
3Reliability
If error correction operations are performed on data distributed across multiple memory rows, then comprehensive error detection and correction is achieved, but frequent row activation and pre-charging operations reduce system efficiency
Solution Approach 1:
The patent performs preliminary grouping of error addresses by their corresponding memory row before executing correction operations. This preliminary action ensures that when the actual correction operations begin, the memory controller already knows which row to access next, eliminating delays caused by dynamic row switching during the correction process.
Solution Approach 2:
The patent segments the correction operations into row-specific batches, processing all errors in one row before moving to the next row. This segmentation reduces the total number of row activation and pre-charging operations compared to processing errors in random order, as each row is activated once and all its associated errors are corrected during that active period.
Data Source
AI summary
An error correction device includes a decoding unit, an error buffer, an error classifying unit and an error correction unit. The decoding unit reads data from a main memory and performs error detection on the data to generate error values and error addresses. Then, the error buffer temporarily stores the error values and the error addresses. The error classifying unit classifies the error addresses stored in the error buffer into a plurality of subclasses, where error values and error addresses which correspond to the same row of the main memory are classified into the same subclass. Finally, the error correction unit performs an error correction on the data stored in the main memory according to the plurality of subclasses. The error correction device therefore can reduce the amount of the change-row operations of the main memory so that the memory efficiency is increased.