Error Correction Encoding with Lane Barrel Shift Interleaving
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Solution Overview
Problem
Conventional error correction encoding methods in digital transmission systems face constraints in parity sequence length, leading to non-uniform allocation ratios between information and parity sequence areas, which limits processing throughput and error correction capability.
Innovation Solution
An error correction encoding method that divides a parallel input sequence into given lanes and performs a barrel shift for each inner frame, ensuring uniform allocation ratios between information and parity sequence areas, thereby improving processing throughput and error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel processing of 512 lines per column is adopted with OTUkV frame, then processing throughput is improved, but the parity sequence length becomes constrained and allocation ratios become non-uniform
Solution Approach 1:
The patent divides the parallel input sequence into multiple lanes (e.g., 512 lines divided into 4 lanes of 128 lines each) and applies independent barrel shifts to each lane. This segmentation allows the system to handle 512-line parallel processing while maintaining uniform allocation ratios within each lane, thus improving throughput without constraining the overall frame structure.
Solution Approach 2:
The patent introduces a new dimension of interleaving by performing barrel shifts within each lane independently. This transforms the problem from a two-dimensional constraint (frame structure) to a three-dimensional solution space by adding the lane dimension, enabling flexible parallel processing while maintaining allocation uniformity.
2Manufacturing precision
If conventional interleaving with uniform allocation is used, then allocation ratios are uniform, but the parity sequence length is constrained
Solution Approach 1:
The patent segments the frame into multiple lanes and applies barrel shifts within each lane. This allows different allocation ratios in different lanes while maintaining uniformity within each lane, thus achieving both precision in allocation and flexibility in overall frame structure.
Solution Approach 2:
The patent introduces dynamic barrel shift operations that can be applied independently to each lane. This dynamic approach allows the system to adapt the interleaving pattern to match the desired parity sequence length while maintaining uniform allocation ratios within each lane, providing both precision and flexibility.
3Productivity
If parallel processing is increased to 512 lines, then processing throughput improves, but device complexity increases
Solution Approach 1:
The patent divides the complex 512-line interleaving operation into four simpler 128-line lane operations. Each lane can be processed independently with its own barrel shift, reducing the complexity of individual operations while achieving the overall 512-line parallel processing throughput.
Solution Approach 2:
The patent combines multiple independent lane operations to achieve the overall interleaving effect. By merging four 128-line lane operations, the system achieves 512-line parallel processing throughput while keeping each individual operation relatively simple and manageable.
Data Source
AI summary
An error correction encoding device includes an outer encoding circuit that performs encoding processing for an outer code and an inner encoding circuit that performs encoding processing for an inner code. The inner encoding circuit includes an inner-encoding input circuit that performs interleaving processing in which a parallel input sequence is divided into lanes and in which a barrel shift is performed for each inner frame in the lanes. Thus, allocation ratios between an information sequence area and a parity sequence area are made uniform.