Error-Correction Matrix Optimization for Fewer Cycles and Encoder Gates
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Solution Overview
Problem
Existing data encoding systems using random or independently optimized matrices for error correction codes face issues such as increased error correction code failures due to incident cycles and excessive encoder gates, leading to inefficiencies in hardware usage and power consumption.
Innovation Solution
The system generates and optimizes a set of matrices using an iteratively-generated combination set, specifically designed to reduce incident cycles and encoder gates, thereby improving error correction code reliability and reducing hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If random matrices are used for error correction codes, then device complexity is reduced, but reliability deteriorates due to incident cycles causing error correction code failures
Solution Approach 1:
The patent applies preliminary action by pre-optimizing matrices to remove incident cycles before they cause errors. The system performs iterative optimization processes in advance to eliminate harmful incident cycles of length 4 or less, ensuring that when matrices are used for encoding, they already have reduced error floors and improved reliability without requiring complex real-time adjustments.
Solution Approach 2:
The patent changes structural parameters of matrices by systematically modifying their configuration to eliminate incident cycles. The optimization process alters matrix parameters such as the positions and values of non-zero elements while maintaining the overall matrix dimensions and code rate, thereby improving reliability without significantly increasing complexity.
2Reliability
If independently optimized matrices are used, then error correction performance is improved, but device complexity increases due to excessive encoder gates
Solution Approach 1:
The patent merges multiple optimization objectives into a unified matrix design process. By simultaneously optimizing for both error correction performance and encoder gate count during the matrix generation process, the system produces matrices that achieve good error floor characteristics without requiring excessive hardware resources, thus resolving the contradiction between performance and complexity.
Solution Approach 2:
The patent optimizes matrix parameters to minimize encoder gate requirements while maintaining error correction performance. The iterative optimization process adjusts matrix parameters to reduce the number of non-zero elements and simplify the encoding structure, thereby reducing the gate count needed for implementation without sacrificing reliability.
3Ease of manufacture
If matrices with many incident cycles are used, then ease of manufacture is improved, but reliability deteriorates due to increased error correction code failures
Solution Approach 1:
The patent applies preliminary action by performing iterative optimization to remove incident cycles before matrices are deployed for encoding. This pre-processing step ensures that matrices have reduced error floors and improved reliability while maintaining relatively simple structures that can be manufactured and implemented without excessive complexity.
Solution Approach 2:
The patent generates multiple candidate matrices and selects or combines them based on their incident cycle characteristics. By creating a pool of optimized matrices through iterative processes and selecting those with fewer incident cycles, the system achieves improved reliability while maintaining ease of manufacture through standardized generation procedures.
4Reliability
If more encoder gates are used, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent optimizes matrix parameters to minimize the number of encoder gates required while maintaining error correction reliability. By carefully controlling matrix structure parameters such as sparsity patterns and non-zero element positions, the system reduces the hardware resources needed for encoding, thereby lowering power consumption without sacrificing reliability.
Solution Approach 2:
The patent extracts and eliminates unnecessary computational operations from the encoding process by removing incident cycles and simplifying matrix structures. This extraction of redundant operations reduces the number of encoder gates needed, thereby reducing power consumption while maintaining the essential error correction functionality.
Data Source
AI summary
A non-transitory computer-readable medium, method and system, the system including processing circuitry. The processing circuitry is to generate a first matrix, perform an incident cycle optimization process using the first matrix to generate a modified first matrix, and perform an encoder gate optimization process using the modified first matrix to generate a further modified first matrix. Processing circuitry is then to generate a second matrix including the further modified first matrix as a submatrix of the second matrix, perform the incident cycle optimization process using the second matrix to generate a modified second matrix, and perform the encoder gate optimization process using the further modified first matrix and the modified second matrix to generate a further modified second matrix. Processing circuitry then configures a transmitting device that receives and encodes transmission data the using the further modified first matrix and further modified second matrix, and transmits the encoded transmission data.