Error Correction Circuit with Targeted Refresh for DRAM Reliability
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Solution Overview
Problem
Semiconductor devices face increased error probability due to faster data transmission speeds, requiring advanced techniques to ensure reliable data transmission, especially during write and read operations in DRAM devices.
Innovation Solution
Incorporating an error correction circuit and refresh control circuit to detect and correct errors in internal data, and to perform additional refresh operations on failed memory cells by replacing faulty word lines with repair lines during specific signal input conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data transmission speed is increased, then operation speed is improved, but error probability increases
Solution Approach 1:
The patent performs preliminary error detection using ECC codes before data is fully transmitted or stored. The error detection code is generated in advance and transmitted with the data, allowing errors to be identified and corrected before they propagate, thus maintaining high transmission speeds while improving reliability.
Solution Approach 2:
The patent introduces error correction codes (ECC) as an intermediary mechanism between the data transmission source and destination. These codes act as a mediator that detects and corrects errors without requiring retransmission, thereby maintaining high data transmission speeds while ensuring data integrity.
2Reliability
If error correction codes are transmitted with data, then data transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the error correction system into separate functional modules: an error detection unit that generates ECC codes, a transmission unit that sends both data and codes, and a correction unit that processes errors. This segmentation allows each module to be optimized independently, reducing overall system complexity while maintaining high reliability.
Solution Approach 2:
The patent implements self-service error correction where the system automatically detects and corrects errors using the transmitted ECC codes without requiring external intervention or complex control logic. The error correction circuit autonomously processes errors, simplifying the overall device architecture while ensuring data integrity.
3Reliability
If additional refresh operations are performed on failed memory cells, then memory cell integrity is maintained, but operation time increases
Solution Approach 1:
The patent applies refresh operations selectively to only those memory cells that have been identified as failed or at risk, rather than performing uniform refresh operations on all memory cells. This localized approach maintains memory cell integrity for problematic cells while minimizing the time impact on the overall memory system.
Solution Approach 2:
The patent performs preliminary identification of failed memory cells through error detection mechanisms before executing refresh operations. By pre-identifying problematic cells, the system can target refresh operations only where needed, avoiding unnecessary time consumption on already functional memory cells while maintaining overall memory reliability.
Data Source
AI summary
A semiconductor device includes an error correction circuit and a refresh control circuit. The error correction circuit is configured to detect an error included in internal data, to generate a failure detection signal, and to correct the error of the internal data. The refresh control circuit is configured to store an address signal for selecting the internal data in response to the failure detection signal. In addition, the refresh control circuit is configured to generate a refresh address signal for activating a word line connected to memory cells storing the internal data from the address signal when a refresh signal is inputted to the refresh control circuit by a predetermined number of times.