Error Correction Circuit for Semiconductor Data Reliability
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Solution Overview
Problem
As semiconductor devices increase operating speed, the probability of errors during data transmission also rises, necessitating a reliable method for error correction that existing technologies have not adequately addressed.
Innovation Solution
A semiconductor system that includes a control circuit, latch circuit, and error correction circuit, capable of generating and testing error correction signals in an error correction test mode, ensuring data reliability by correcting errors in external data and detecting the correctness of these corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of the semiconductor device is increased to improve productivity, then the data transmission speed increases, but the probability of errors during data transmission increases, worsening reliability
Solution Approach 1:
The patent introduces an error correction circuit as an intermediary component between the data transmission path and the output. This circuit includes an error correction code generator that creates redundancy bits and an error corrector that uses these bits to detect and correct errors in the transmitted data, thereby maintaining reliability despite increased transmission speeds
Solution Approach 2:
The patent changes the parameter structure of data transmission by adding error correction codes and parity bits to the original data. This transforms the data from a simple binary stream into a structured format with embedded error detection and correction capabilities, allowing the system to maintain reliability while operating at higher speeds
2Reliability
If error correction codes are added to ensure data reliability, then the reliability of data transmission is improved, but the device complexity increases due to additional circuits
Solution Approach 1:
The error correction functionality is segmented into distinct modular components: an error correction code generator that processes input data separately, a latch circuit that stores data and parity bits separately, and an error corrector that processes errors independently. This segmentation allows each component to be optimized independently and simplifies the overall system design
Solution Approach 2:
The error correction code is generated preliminarily during the write operation before data is stored in the latch circuit. This preliminary generation of redundancy bits allows the error correction mechanism to be prepared in advance, reducing the complexity of real-time error handling during read operations
Data Source
AI summary
A semiconductor device includes a control circuit configured to generate an input enable signal, an output enable signal, a latch control signal, and an error correction control signal based on a write control signal, a write check command, and a read check command for performing an error correction test mode; a latch circuit configured to generate latch data, a latch parity, and a latch masking signal by latching input data, an input parity, and an input masking signal and configured to re-store corrected data as the latch data, during a period in which the latch control signal is enabled; and an error correction circuit configured to generate the corrected data by correcting an error, included in the latch data, based on the latch data, the latch parity and the latch masking signal during a period in which the error correction control signal is enabled.