Error Correction Circuit for Two-Symbol Parallel Decoding
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Solution Overview
Problem
As communication speeds increase and data throughput rises, the number of error bits in information data also increases, leading to higher error correction latency in existing error correction systems.
Innovation Solution
An error correction decoder that corrects errors in units of two consecutive symbols, utilizing a syndrome generation circuit, error location determination circuit, and error value determination circuit to reduce latency by determining error locations and values in parallel for groups of two consecutive symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed on all symbols sequentially, then error correction accuracy is maintained, but error correction latency increases
Solution Approach 1:
The error correction process is segmented into independent units of two consecutive symbols. The syndrome generation circuit generates syndromes for each unit, and the error location determination circuit processes each unit separately to determine error locations. This segmentation enables parallel processing of multiple symbol units simultaneously, reducing overall error correction latency while maintaining accuracy through systematic processing of each segment
Solution Approach 2:
The syndrome generation circuit performs preliminary calculation of syndromes for groups of two consecutive symbols before error location determination. By pre-calculating syndromes S1-S6 for each symbol unit in advance, the system prepares error correction data upfront, enabling faster error location determination and correction execution, thus reducing total error correction latency
2Productivity
If the number of error bits increases due to higher data throughput, then data transmission capacity is improved, but error correction complexity increases
Solution Approach 1:
The error correction circuit divides the data stream into discrete units of two consecutive symbols, processing each unit independently through syndrome generation and error location determination. This segmentation transforms the complex problem of correcting multiple error bits in large data streams into manageable sub-problems, reducing overall error correction complexity while maintaining high data throughput capability
Solution Approach 2:
The system changes the parameter of error correction granularity from individual symbols to units of two consecutive symbols. This parameter change optimizes the balance between error correction complexity and effectiveness, allowing the syndrome generation circuit to efficiently handle increased error bits from higher throughput while keeping computational complexity manageable through structured processing
Data Source
AI summary
An error correction device includes a syndrome generation circuit configured to output a first syndrome, a second syndrome, a third syndrome, a fourth syndrome, a fifth syndrome, and a sixth syndrome for data, an error location determination circuit configured to determine a coefficient of a first error location polynomial, based on the first syndrome, the second syndrome, and the third syndrome, determine a coefficient of a second error location polynomial, based on the fourth syndrome, the fifth syndrome, and the sixth syndrome, and obtain locations of errors included in the data in units of two consecutive symbols, based on the first error location polynomial and the second error location polynomial, and an error value determination circuit configured to predetermine values of the errors in units of two consecutive symbols, based on the first syndrome and the second syndrome.