Iterative Error Correction Decoder With Flipping Threshold Logic
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Solution Overview
Problem
Current memory systems face challenges in reducing hardware complexity and power consumption while ensuring reliable error correction, particularly due to the complexity of existing error correction decoders and the interference between adjacent memory cells.
Innovation Solution
An error correction decoder is designed using an iterative decoding scheme with a flipping function value generator and comparator to determine whether to flip hard decision values based on the difference between unsatisfied and satisfied check nodes, reducing hardware complexity and power consumption by optimizing the flipping function value generation and comparison process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction decoding is used, then data reliability is maintained, but hardware complexity increases
Solution Approach 1:
The error correction decoder is divided into multiple independent modules: a hard decision value storage unit, a flipping function value generation unit, and a comparison unit. Each module performs a specific function, allowing the system to maintain reliable error correction while reducing overall hardware complexity through functional segmentation.
Solution Approach 2:
The patent extracts the essential flipping decision logic from complex conventional decoders by isolating the flipping function value generation and comparison operations. This extraction allows the system to maintain error correction reliability while significantly reducing hardware complexity by implementing only the necessary components.
2Reliability
If conventional error correction decoding is used, then data reliability is maintained, but power consumption increases
Solution Approach 1:
By segmenting the decoder into discrete functional units (storage unit, generation unit, comparison unit), the system can power individual modules selectively, reducing overall power consumption while maintaining the reliability needed for error correction.
Solution Approach 2:
The patent extracts and implements only the essential flipping decision logic required for error correction, eliminating unnecessary computational operations. This extraction reduces power consumption by performing only the minimum required operations to maintain data reliability.
3Reliability
If iterative decoding scheme is implemented, then error correction performance is improved, but hardware complexity increases
Solution Approach 1:
The iterative decoding scheme is implemented through segmented functional modules that can be reused across iterations. The hard decision value storage unit, flipping function value generation unit, and comparison unit form a compact iterative structure that improves error correction performance without proportionally increasing hardware complexity.
4Use of energy by moving object
If flipping function value generation is optimized, then power consumption is reduced, but hardware complexity increases
Solution Approach 1:
The patent extracts the core flipping function value generation logic into a dedicated, simplified module that performs only the essential calculations. This extraction reduces power consumption by eliminating redundant computations while maintaining manageable hardware complexity through focused functional design.
Data Source
AI summary
Provided herein is an error correction decoder and a memory system having the same. The error correction decoder includes a memory configured to store a hard decision value of a variable node. The decoder further includes a flipping function value generator configured to generate, in an i-th iteration, a first value based on a number of unsatisfied check nodes (UCNs) corresponding to the variable node, and to generate a flipping function value as (i) a difference between the first value and an offset value or (ii) a set value, wherein i is a non-negative integer. The decoder also includes a comparator configured to output, in the i-th iteration, a first signal indicating whether to flip or not flip the hard decision value of the variable node in the memory based on comparing the flipping function value to a flipping threshold value.