Error Detecting Circuit for Catastrophic Error Signal Differentiation
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Solution Overview
Problem
New generation processors, such as Xeon 5500 and 5600 series, integrate machine check and internal error signals into a catastrophic error signal (CATERR#), but conventional baseboard management controllers (BMC) and BIOS cannot process this signal to restore system operation effectively.
Innovation Solution
A computer system with an error detecting circuit that generates internal and machine error reset signals based on the catastrophic error signal, utilizing a south bridge chip to reboot the system and a baseboard management controller to log error events, incorporating inverter and filter units to differentiate between internal and machine errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the functions of machine check error signal and internal error signal are integrated into a catastrophic error signal in new generation processors, then the processor structure is simplified, but conventional baseboard management controllers and BIOS cannot process the signal to restore system operation
Solution Approach 1:
The patent introduces an error detecting circuit as an intermediary component between the processor and the baseboard management controller/BIOS. This circuit receives the catastrophic error signal, distinguishes between machine check errors and internal errors through timing analysis, and generates appropriate reset signals. This mediator enables systems with conventional BMCs and BIOS to properly handle the integrated catastrophic error signal from new generation processors.
2Measurement precision
If the error detecting circuit uses timing discrimination to differentiate between internal errors and machine check errors, then error identification accuracy is improved, but the response time for system restoration is increased
Solution Approach 1:
The patent changes the timing parameter of error signal processing by introducing two distinct time thresholds: a first predetermined time for internal error detection and a second predetermined time (longer than the first) for machine check error detection. By adjusting these time parameters, the system achieves accurate error differentiation while minimizing restoration delay - internal errors trigger immediate reset after the first threshold, while machine check errors allow longer for potential software recovery before reset at the second threshold.
Data Source
AI summary
A computer system including a first processor, an error detecting circuit and a south bridge chip is provided. The first processor outputs a first catastrophic error signal. The error detecting circuit is coupled to the first processor to receive the first catastrophic error signal. When the first catastrophic error signal changes to a first level and is maintained for a period exceeding a first predetermined time, the error detecting circuit outputs an internal error reset signal. When the first catastrophic error signal changes to a first level and passes a second predetermined time, the error detecting circuit outputs a machine error reset signal. Here, the second predetermined time is greater than the first predetermined time. The south bridge chip is coupled to the error detecting circuit and reboots the computer system according the internal error reset signal or the machine error reset signal.