Error Detecting Circuit for Semiconductor Apparatus Fail Detection
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Solution Overview
Problem
Current semiconductor apparatuses face challenges in efficiently detecting and repairing errors in error detecting circuits due to limitations in fail detection rates and repair efficiency, particularly in compressed test scenarios where incorrect determinations can occur.
Innovation Solution
The implementation of a semiconductor apparatus with a fail detection system that includes multiple fail detection units, a common fail detection unit, and a fail determination unit, which combines and processes test data signals from multiple blocks to accurately detect failures and determine the need for repair, utilizing logic operations like XNOR and AND to generate fail detection signals and enable efficient repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a compressed test is used to reduce test time, then productivity is improved, but measurement precision deteriorates due to potential incorrect fail detections
Solution Approach 1:
The semiconductor apparatus is divided into multiple blocks (first block, second block, etc.), each with dedicated fail detection units. This segmentation allows parallel testing of multiple blocks while maintaining individual detection accuracy, resolving the contradiction between compressed test speed and detection precision.
Solution Approach 2:
A common fail detection unit serves as an intermediary that receives test data from multiple blocks and performs unified fail detection. This intermediary structure enables coordinated detection across blocks, ensuring accurate fail identification while maintaining compressed test efficiency.
2Measurement precision
If multiple fail detection units are used to improve fail detection accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The common fail detection unit is designed with multi-functionality, serving as the detection unit for multiple blocks simultaneously. This universal design reduces the total number of detection units needed, improving fail detection accuracy while limiting the increase in device complexity.
Solution Approach 2:
Multiple test data signals from different blocks are combined and fed into a common fail detection unit. This merging approach consolidates detection resources, achieving comprehensive fail detection coverage without proportionally increasing circuit complexity.
3Measurement precision
If dedicated fail detection units are assigned to each block, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The common fail detection unit performs universal detection functions for multiple blocks, eliminating the need for separate dedicated detection units for each block. This approach maintains block-specific detection precision while reducing overall device complexity by sharing detection resources.
Data Source
AI summary
An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, and levels of the 2-bit first test data signals and the 2-bit second test data signals are the same with each other.