Error Detection Circuit Fault Injection Logic

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Solution Overview

Problem

Conventional systems for testing error detection circuits in automotive ECUs are costly and ineffective in detecting malfunctions during the operational life of the circuits, requiring additional equipment and being limited to post-manufacturing testing.

Innovation Solution

A system that injects faults into error detection circuits using a NOT gate, AND gate, and multiplexer to generate non-identical output signals, allowing the error detection circuit to detect errors and triggering an alert, which can be activated by the ECU during operation to identify faults in real-time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional testing schemes using microcontrollers and robotic arm mechanisms are used, then fault injection and capture can be performed, but manufacturing costs increase significantly

Engineering Contradiction:
Improvefault detection capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The error detection circuit performs self-testing by injecting faults into itself through the integrated logic gates (NOT gate, AND gate, and multiplexer) rather than requiring external testing equipment. The circuit monitors its own outputs and generates error signals when faults are detected, eliminating the need for costly microcontrollers and robotic mechanisms.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The testing functionality is merged directly into the error detection circuit by integrating the fault injection logic (NOT gate, AND gate, multiplexer) within the same circuit. This combination eliminates the need for separate testing equipment and reduces manufacturing costs while maintaining fault detection capability.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If post-manufacturing testing is performed using additional testing equipment, then faults can be detected before shipping, but testing during operational life becomes difficult

Engineering Contradiction:
Improvefault detection timingVSAvoidtesting system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error detection circuit continuously performs self-testing during operational life without requiring external testing equipment. The integrated fault injection mechanism allows the circuit to monitor itself in real-time, enabling fault detection during both manufacturing and operational phases.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The error detection circuit provides continuous fault detection capability throughout the entire operational life of the system. The testing function is not limited to post-manufacturing checks but operates continuously, ensuring faults are detected whenever they occur.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If redundant channel with processor core and bus is used for monitoring, then error detection capability is improved, but device complexity and cost increase

Engineering Contradiction:
Improveerror detection capabilityVSAvoidmonitoring system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of using a full redundant processor core and bus system for monitoring, the invention implements error detection capability locally within the error detection circuit itself. The fault injection logic (NOT gate, AND gate, multiplexer) is integrated directly into the circuit being tested, providing localized monitoring without requiring complex redundant processing systems.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8868989B2System for testing error detection circuits
Publication Date: 2014.10.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8868989B2 patent drawing
  • US8868989B2 patent drawing
  • US8868989B2 patent drawing

AI summary

A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.