Error Detection Code Generation Using Segmented CRC Logic
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Solution Overview
Problem
Conventional error detection code generation circuits in semiconductor circuits require extended time due to the need for data bus inversion function operations, degrading system performance.
Innovation Solution
The proposed method generates virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit that utilizes even and odd number information to produce error detection codes independently of the data bus inversion unit, reducing the overall generation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection codes are generated using conventional CRC logic that processes all 64-bit data and DBI flags sequentially, then accurate error detection is achieved, but the generation time is extended
Solution Approach 1:
The 64-bit data is divided into multiple 8-bit groups, and error detection codes are generated for each group independently using segmented CRC logic. This allows parallel processing of different data groups, reducing the overall generation time while maintaining accurate error detection for the complete data set
Solution Approach 2:
Error detection codes are generated preliminarily for each 8-bit data group before the complete 64-bit data processing is finished. These preliminary codes are then combined to form the final error detection code, enabling early computation and reducing the critical path delay
2Object-affected harmful factors
If data bus inversion function is implemented to reduce switching noise, then signal integrity is improved, but the system complexity increases
Solution Approach 1:
The data bus inversion function is applied segmentally to 8-bit groups rather than the entire 64-bit data bus. This segmentation reduces the switching activity on the inverted groups and allows the inversion logic to be distributed across multiple smaller units, reducing peak current consumption and simplifying the control logic
Solution Approach 2:
Data bus inversion is applied selectively to only those 8-bit groups that require it based on their error detection code, rather than inverting the entire 64-bit bus. This partial application reduces the number of switched signals and minimizes the impact on system complexity
Data Source
AI summary
An apparatus for generating error detection codes can include an error detection code generation unit configured to generate virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit configured to generate error detection codes using even and odd number information which define whether the number of data associated with the generation of the error detection codes is even or odd, DBI information associated with the even and odd number information, and the virtual error detection codes.